mirror of https://github.com/m-labs/artiq.git
cri: add buffer space request protocol
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@ -113,7 +113,7 @@ class RTPacketSatellite(Module):
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rx_plm.types["echo_request"]: echo_req.eq(1),
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rx_plm.types["set_time"]: NextState("SET_TIME"),
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rx_plm.types["write"]: NextState("WRITE"),
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rx_plm.types["buffer_space_request"]: NextState("BUFFER_SPACE"),
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rx_plm.types["buffer_space_request"]: NextState("BUFFER_SPACE_REQUEST"),
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rx_plm.types["read_request"]: NextState("READ_REQUEST"),
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"default": self.unknown_packet_type.eq(1)
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})
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@ -142,10 +142,16 @@ class RTPacketSatellite(Module):
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)
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)
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)
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rx_fsm.act("BUFFER_SPACE_REQUEST",
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self.cri.cmd.eq(cri.commands["get_buffer_space"]),
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NextState("BUFFER_SPACE")
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)
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rx_fsm.act("BUFFER_SPACE",
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buffer_space_set.eq(1),
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buffer_space_update.eq(1),
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NextState("INPUT")
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If(self.cri.o_buffer_space_valid,
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buffer_space_set.eq(1),
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buffer_space_update.eq(1),
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NextState("INPUT")
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)
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)
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rx_fsm.act("READ_REQUEST",
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@ -13,11 +13,13 @@ from misoc.interconnect.csr import *
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commands = {
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"nop": 0,
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"write": 1,
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# i_status should have the "wait for status" bit set until
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# an event is available, or timestamp is reached.
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"read": 2
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"read": 2,
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# targets must assert o_buffer_space_valid in response
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# to this command
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"get_buffer_space": 3
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}
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@ -32,8 +34,11 @@ layout = [
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# o_status bits:
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# <0:wait> <1:underflow> <2:link error>
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("o_status", 3, DIR_S_TO_M),
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# targets may optionally report a pessimistic estimate of the number
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# of outputs events that can be written without waiting.
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# pessimistic estimate of the number of outputs events that can be
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# written without waiting.
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# this feature may be omitted on systems without DRTIO.
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("o_buffer_space_valid", 1, DIR_S_TO_M),
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("o_buffer_space", 16, DIR_S_TO_M),
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("i_data", 32, DIR_S_TO_M),
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@ -55,7 +55,10 @@ class SED(Module):
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self.comb += i.eq(o)
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if report_buffer_space:
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self.comb += self.cri.o_buffer_space.eq(self.fifos.buffer_space)
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self.comb += [
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self.cri.o_buffer_space_valid.eq(1),
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self.cri.o_buffer_space.eq(self.fifos.buffer_space)
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]
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@property
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def cri(self):
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