M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

rtio: fix CRI CSRs

This commit is contained in:
Sebastien Bourdeauducq 2016-11-22 22:57:04 +08:00
parent 9acc7d135e
commit aa00627c0e
1 changed files with 0 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
artiq/gateware/rtio/cri.py
View File

@ -116,9 +116,3 @@ class KernelInitiator(Module, AutoCSR):
self.o_data.we.eq(self.o_timestamp.re), self.o_data.we.eq(self.o_timestamp.re),
] ]
self.sync += If(self.counter_update.re, self.counter.status.eq(self.cri.counter)) self.sync += If(self.counter_update.re, self.counter.status.eq(self.cri.counter))
def get_csrs(self):
return []
def get_kernel_csrs(self):
return AutoCSR.get_csrs(self)