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slave_fpga: add another check

This commit is contained in:
Robert Jördens 2018-06-12 16:23:13 +08:00 committed by Robert Jördens
parent a143e238a8
commit a9d97101fc
1 changed files with 3 additions and 1 deletions
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4
artiq/firmware/libboard_artiq/slave_fpga.rs
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@ -60,6 +60,9 @@ pub fn load() -> Result<(), &'static str> {
if csr::slave_fpga_cfg::in_read() & INIT_B_BIT == 0 {
return Err("Did not exit INIT after releasing PROGRAM");
}
if csr::slave_fpga_cfg::in_read() & DONE_BIT != 0 {
return Err("DONE high despite PROGRAM");
}
for i in slice::from_raw_parts(GATEWARE.offset(8), length) {
shift_u8(*i);
@ -72,7 +75,6 @@ pub fn load() -> Result<(), &'static str> {
while csr::slave_fpga_cfg::in_read() & DONE_BIT == 0 {
if clock::get_ms() > t + 100 {
error!("Timeout wating for DONE after loading");
error!("Boards not populated correctly?");
return Err("Not DONE");
}
shift_u8(0xff);