From a9a25f26054906d7ce03b7dff900cb7ad6384ffd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Tue, 12 Jun 2018 20:00:12 +0200 Subject: [PATCH] sayma_rtm: drive ref_lo_clk_sel, and set clk muxes early --- artiq/firmware/libboard_artiq/hmc830_7043.rs | 4 +++- artiq/gateware/targets/sayma_rtm.py | 4 +++- conda/artiq-dev/meta.yaml | 2 +- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/artiq/firmware/libboard_artiq/hmc830_7043.rs b/artiq/firmware/libboard_artiq/hmc830_7043.rs index c33131f54..e0ab1adc3 100644 --- a/artiq/firmware/libboard_artiq/hmc830_7043.rs +++ b/artiq/firmware/libboard_artiq/hmc830_7043.rs @@ -4,13 +4,15 @@ mod clock_mux { const CLK_SRC_EXT_SEL : u8 = 1 << 0; const REF_CLK_SRC_SEL : u8 = 1 << 1; const DAC_CLK_SRC_SEL : u8 = 1 << 2; + const REF_LO_CLK_SEL : u8 = 1 << 3; pub fn init() { unsafe { csr::clock_mux::out_write( 1*CLK_SRC_EXT_SEL | // use ext clk from sma 1*REF_CLK_SRC_SEL | - 1*DAC_CLK_SRC_SEL); + 1*DAC_CLK_SRC_SEL | + 0*REF_LO_CLK_SEL); } } } diff --git a/artiq/gateware/targets/sayma_rtm.py b/artiq/gateware/targets/sayma_rtm.py index ac376f5d2..e3fca7e3e 100755 --- a/artiq/gateware/targets/sayma_rtm.py +++ b/artiq/gateware/targets/sayma_rtm.py @@ -124,7 +124,9 @@ class SaymaRTM(Module): self.submodules.clock_mux = gpio.GPIOOut(Cat( platform.request("clk_src_ext_sel"), platform.request("ref_clk_src_sel"), - platform.request("dac_clk_src_sel"))) + platform.request("dac_clk_src_sel"), + platform.request("ref_lo_clk_sel")), + reset_out=0b0111) csr_devices.append("clock_mux") # UART loopback diff --git a/conda/artiq-dev/meta.yaml b/conda/artiq-dev/meta.yaml index 2243461ed..c19a7f3b0 100644 --- a/conda/artiq-dev/meta.yaml +++ b/conda/artiq-dev/meta.yaml @@ -14,7 +14,7 @@ requirements: run: - python >=3.5.3,<3.6 - setuptools 33.1.1 - - migen 0.7 py35_44+gitca28f4e + - migen 0.7 py35_46+git5947224c - misoc 0.11 py35_20+git2436a68d - jesd204b 0.7 - microscope