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coredevice/zotino: add (#969)
* Replace ad5360 driver with a ad53xx driver, designed to have a nicer interface Add Zotino driver and add to opticlock target for Kasli Test Zotino on hw: - Verify all timings on the hardware with a scope - Verify that we can correctly set and read back all registers in a loop (checks for SI and driver issues) - check we can set LEDs correctly - check calibration routine + all si unit functions with a good DVM - look at DAC transitions on a scope (while triggering of a TTL) on persist to check there are no LDAC glitches etc To do: update examples and e.g. KC705 device db.
This commit is contained in:
hartytp
parent
1553fc8c7d
commit
a992a672d9
@ -1,190 +0,0 @@
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"""
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Driver for the AD5360 DAC on RTIO.
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Output event replacement is not supported and issuing commands at the same
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time is an error.
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"""
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from artiq.language.core import (kernel, portable, delay_mu, delay, now_mu,
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at_mu)
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from artiq.language.units import ns, us
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from artiq.coredevice import spi2 as spi
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# Designed from the data sheets and somewhat after the linux kernel
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# iio driver.
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_AD5360_SPI_CONFIG = (0*spi.SPI_OFFLINE | 1*spi.SPI_END |
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0*spi.SPI_INPUT | 0*spi.SPI_CS_POLARITY |
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0*spi.SPI_CLK_POLARITY | 1*spi.SPI_CLK_PHASE |
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0*spi.SPI_LSB_FIRST | 0*spi.SPI_HALF_DUPLEX)
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_AD5360_CMD_DATA = 3 << 22
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_AD5360_CMD_OFFSET = 2 << 22
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_AD5360_CMD_GAIN = 1 << 22
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_AD5360_CMD_SPECIAL = 0 << 22
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@portable
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def _AD5360_WRITE_CHANNEL(c):
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return (c + 8) << 16
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_AD5360_SPECIAL_NOP = 0 << 16
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_AD5360_SPECIAL_CONTROL = 1 << 16
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_AD5360_SPECIAL_OFS0 = 2 << 16
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_AD5360_SPECIAL_OFS1 = 3 << 16
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_AD5360_SPECIAL_READ = 5 << 16
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@portable
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def _AD5360_READ_CHANNEL(ch):
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return (ch + 8) << 7
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_AD5360_READ_X1A = 0x000 << 7
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_AD5360_READ_X1B = 0x040 << 7
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_AD5360_READ_OFFSET = 0x080 << 7
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_AD5360_READ_GAIN = 0x0c0 << 7
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_AD5360_READ_CONTROL = 0x101 << 7
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_AD5360_READ_OFS0 = 0x102 << 7
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_AD5360_READ_OFS1 = 0x103 << 7
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class AD5360:
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"""
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Support for the Analog devices AD53[67][0123]
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multi-channel Digital to Analog Converters
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:param spi_device: Name of the SPI bus this device is on.
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:param ldac_device: Name of the TTL device that LDAC is connected to
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(optional). Needs to be explicitly initialized to high.
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:param chip_select: Value to drive on the chip select lines
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during transactions.
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:param div_write: SPI clock divider during writes
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:param div_read: SPI clock divider during reads
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"""
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kernel_invariants = {"bus", "core", "chip_select", "div_read", "div_write"}
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def __init__(self, dmgr, spi_device, ldac_device=None, chip_select=1,
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div_write=4, div_read=7):
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self.core = dmgr.get("core")
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self.bus = dmgr.get(spi_device)
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if ldac_device is not None:
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self.ldac = dmgr.get(ldac_device)
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self.chip_select = chip_select
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# write: 2*8ns >= 10ns = t_6 (clk falling to cs_n rising)
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# 4*8ns >= 20ns = t_1 (clk cycle time)
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self.div_write = div_write
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# read: 4*8*ns >= 25ns = t_22 (clk falling to miso valid)
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self.div_read = div_read
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@kernel
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def setup_bus(self):
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"""Configure the SPI bus and the SPI transaction parameters
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for this device. This method has to be called before any other method
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if the bus has been used to access a different device in the meantime.
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This method advances the timeline by one coarse RTIO cycle.
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"""
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self.bus.set_config_mu(_AD5360_SPI_CONFIG, 24, self.div_write,
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self.chip_select)
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@kernel
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def write(self, data):
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"""Write 24 bits of data.
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This method advances the timeline by the duration of the SPI transfer
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and the required CS high time.
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"""
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self.bus.write(data << 8)
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delay_mu(self.bus.ref_period_mu) # get to 20ns min cs high
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@kernel
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def write_offsets(self, value=0x1fff):
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"""Write the OFS0 and OFS1 offset DACs.
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This method advances the timeline by twice the duration of
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:meth:`write`.
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:param value: Value to set both offset registers to.
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"""
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value &= 0x3fff
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self.write(_AD5360_CMD_SPECIAL | _AD5360_SPECIAL_OFS0 | value)
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self.write(_AD5360_CMD_SPECIAL | _AD5360_SPECIAL_OFS1 | value)
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@kernel
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def write_channel(self, channel=0, value=0, op=_AD5360_CMD_DATA):
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"""Write to a channel register.
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This method advances the timeline by the duration of :meth:`write`.
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:param channel: Channel number to write to.
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:param value: 16 bit value to write to the register.
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:param op: Operation to perform, one of :const:`_AD5360_CMD_DATA`,
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:const:`_AD5360_CMD_OFFSET`, :const:`_AD5360_CMD_GAIN`
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(default: :const:`_AD5360_CMD_DATA`).
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"""
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channel &= 0x3f
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value &= 0xffff
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self.write(op | _AD5360_WRITE_CHANNEL(channel) | value)
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@kernel
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def read_channel_sync(self, channel=0, op=_AD5360_READ_X1A):
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"""Read a channel register.
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This method advances the timeline by the duration of two :meth:`write`
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plus two coarse RTIO cycles.
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:param channel: Channel number to read from.
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:param op: Operation to perform, one of :const:`_AD5360_READ_X1A`,
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:const:`_AD5360_READ_X1B`, :const:`_AD5360_READ_OFFSET`,
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:const:`_AD5360_READ_GAIN` (default: :const:`_AD5360_READ_X1A`).
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:return: The 16 bit register value.
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"""
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channel &= 0x3f
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self.write(_AD5360_CMD_SPECIAL | _AD5360_SPECIAL_READ | op |
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_AD5360_READ_CHANNEL(channel))
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self.bus.set_config_mu(_AD5360_SPI_CONFIG | spi.SPI_INPUT, 24,
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self.div_read, self.chip_select)
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delay(270*ns) # t_21 min sync high in readback
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self.write(_AD5360_CMD_SPECIAL | _AD5360_SPECIAL_NOP)
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self.bus.set_config_mu(_AD5360_SPI_CONFIG, 24,
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self.div_write, self.chip_select)
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return self.bus.read() & 0xffff
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@kernel
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def load(self):
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"""Pulse the LDAC line.
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This method advances the timeline by two RTIO clock periods (16 ns).
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"""
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self.ldac.off()
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# t13 = 10ns ldac pulse width low
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delay_mu(2*self.bus.ref_period_mu)
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self.ldac.on()
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@kernel
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def set(self, values, op=_AD5360_CMD_DATA):
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"""Write to several channels and pulse LDAC to update the channels.
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This method does not advance the timeline. Write events are scheduled
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in the past. The DACs will synchronously start changing their output
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levels `now`.
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:param values: List of 16 bit values to write to the channels.
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:param op: Operation to perform, one of :const:`_AD5360_CMD_DATA`,
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:const:`_AD5360_CMD_OFFSET`, :const:`_AD5360_CMD_GAIN`
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(default: :const:`_AD5360_CMD_DATA`).
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"""
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t0 = now_mu()
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# t10 max busy low for one channel
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t_10 = self.core.seconds_to_mu(1.5*us)
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# compensate all delays that will be applied
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delay_mu(-t_10-len(values)*(
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self.bus.ref_period_mu + self.bus.xfer_duration_mu))
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for i in range(len(values)):
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self.write_channel(i, values[i], op)
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delay_mu(t_10)
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self.load()
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at_mu(t0)
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328
artiq/coredevice/ad53xx.py
Normal file
328
artiq/coredevice/ad53xx.py
Normal file
@ -0,0 +1,328 @@
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""""RTIO driver for the Analog Devices AD53[67][0123] family of multi-channel
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Digital to Analog Converters.
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Output event replacement is not supported and issuing commands at the same
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time is an error.
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"""
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# Designed from the data sheets and somewhat after the linux kernel
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# iio driver.
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from artiq.language.core import (kernel, portable, delay_mu, delay, now_mu,
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at_mu)
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from artiq.language.units import ns
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from artiq.coredevice import spi2 as spi
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SPI_AD53XX_CONFIG = (0*spi.SPI_OFFLINE | 1*spi.SPI_END |
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0*spi.SPI_INPUT | 0*spi.SPI_CS_POLARITY |
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0*spi.SPI_CLK_POLARITY | 1*spi.SPI_CLK_PHASE |
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0*spi.SPI_LSB_FIRST | 0*spi.SPI_HALF_DUPLEX)
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AD53XX_CMD_DATA = 3 << 22
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AD53XX_CMD_OFFSET = 2 << 22
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AD53XX_CMD_GAIN = 1 << 22
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AD53XX_CMD_SPECIAL = 0 << 22
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AD53XX_SPECIAL_NOP = 0 << 16
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AD53XX_SPECIAL_CONTROL = 1 << 16
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AD53XX_SPECIAL_OFS0 = 2 << 16
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AD53XX_SPECIAL_OFS1 = 3 << 16
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AD53XX_SPECIAL_READ = 5 << 16
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AD53XX_READ_X1A = 0X000 << 7
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AD53XX_READ_X1B = 0X040 << 7
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AD53XX_READ_OFFSET = 0X080 << 7
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AD53XX_READ_GAIN = 0X0C0 << 7
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AD53XX_READ_CONTROL = 0X101 << 7
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AD53XX_READ_OFS0 = 0X102 << 7
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AD53XX_READ_OFS1 = 0X103 << 7
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@portable
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def ad53xx_cmd_write_ch(channel, value, op):
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"""Returns the word that must be written to the DAC to set a DAC
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channel register to a given value.
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:param channel: DAC channel to write to (8 bits)
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:param value: 16-bit value to write to the register
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:param op: The channel register to write to, one of
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:const:`AD53XX_CMD_DATA`, :const:`AD53XX_CMD_OFFSET` or
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:const:`AD53XX_CMD_GAIN`.
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:return: The 24-bit word to be written to the DAC, aligned as the 24 MSB of
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a 32-bit integer, ready to be transferred directly by the SPI core.
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"""
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return (op | ((channel & 0x3f) + 8) << 16 | (value & 0xffff)) << 8
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@portable
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def ad53xx_cmd_read_ch(channel, op):
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"""Returns the word that must be written to the DAC to read a given
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DAC channel register.
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:param channel: DAC channel to read (8 bits)
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:param op: The channel register to read, one of
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:const:`AD53XX_CMD_DATA`, :const:`AD53XX_CMD_OFFSET` or
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:const:`AD53XX_CMD_GAIN`
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:return: The 24-bit word to be written to the DAC, aligned as the 24 MSB of
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a 32-bit integer, ready to be transferred directly by the SPI core.
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"""
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return (AD53XX_CMD_SPECIAL | AD53XX_SPECIAL_READ | op |
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(((channel & 0x3f) + 8) << 7)) << 8
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@portable
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def voltage_to_mu(voltage, offset_dacs=8192, vref=5.):
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"""Returns the DAC register value required to produce a given output
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voltage, assuming offset and gain errors have been trimmed out.
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:param voltage: Voltage
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:param offset_dacs: Register value for the two offset DACs (default
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:0x1555)
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:param vref: DAC reference voltage (default: 5.)
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"""
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return int(round(0x10000*(voltage/(4.*vref)) + offset_dacs*0x4))
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@portable
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def offset_to_mu(voltage, offset_dacs=8192, vref=5.):
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"""Returns the offset register value required to produce a given voltage
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when the DAC register is set to mid-scale.
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An offset of V can be used to trim out a DAC offset error of -V.
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:param voltage: Offset voltage
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:param offset_dacs: Register value for the two offset DACs (default
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:0x1555)
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:param vref: DAC reference voltage (default: 5.)
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"""
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return int(round(0x10000*(voltage/(4.*vref)) + offset_dacs*0x4))
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class AD53xx:
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"""Analog devices AD53[67][0123] family of multi-channel Digital to Analog
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Converters.
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:param spi_device: SPI bus device name
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:param ldac_device: LDAC RTIO TTLOut channel name
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:param clr_device: CLR RTIO TTLOut channel name
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:param chip_select: Value to drive on SPI chip select lines during
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transactions (default: 1)
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:param div_write: SPI clock divider for write operations (default: 4,
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50MHz max SPI clock with {t_high, t_low} >=8ns)
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:param div_read: SPI clock divider for read operations (default: 8, not
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optimized for speed, but cf data sheet t22: 25ns min SCLK edge to SDO
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valid)
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:param vref: DAC reference voltage (default: 5.)
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:param offset_dacs: Initial register value for the two offset DACs, device
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dependent and must be set correctly for correct voltage to mu conversions
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(default: 8192)
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:param core_device: Core device name (default: "core")
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"""
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kernel_invariants = {"bus", "ldac", "clr", "chip_select", "div_write",
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"div_read", "vref", "core"}
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def __init__(self, dmgr, spi_device, ldac_device, clr_device,
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chip_select=1, div_write=4, div_read=8, vref=5.,
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offset_dacs=8192, core="core"):
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self.bus = dmgr.get(spi_device)
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self.ldac = dmgr.get(ldac_device)
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self.clr = dmgr.get(clr_device)
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self.chip_select = chip_select
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self.div_write = div_write
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self.div_read = div_read
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self.vref = vref
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self.offset_dacs = offset_dacs
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self.core = dmgr.get(core)
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@kernel
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def init(self):
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"""Configures the SPI bus, drives LDAC and CLR high and programmes
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the offset DACss.
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This method must be called before any other method at start-up or if
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the SPI bus has been accessed by another device.
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This method advances the timeline by one coarse RTIO cycle.
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"""
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self.ldac.on()
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self.clr.on()
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self.bus.set_config_mu(SPI_AD53XX_CONFIG, 24, self.div_write,
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self.chip_select)
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self.write_offset_dacs_mu(self.offset_dacs)
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@kernel
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def read_reg(self, channel=0, op=AD53XX_READ_X1A):
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"""Read a DAC register.
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This method advances the timeline by the duration of two SPI transfers
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plus two RTIO coarse cycles.
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:param channel: Channel number to read from (default :0)
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:param op: Operation to perform, one of :const:`AD53XX_READ_X1A`,
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:const:`AD53XX_READ_X1B`, :const:`AD53XX_READ_OFFSET`,
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:const:`AD53XX_READ_GAIN` (default: :const:`AD53XX_READ_X1A`).
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:return: The 16 bit register value
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"""
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self.bus.write(ad53xx_cmd_read_ch(channel, op))
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self.bus.set_config_mu(SPI_AD53XX_CONFIG | spi.SPI_INPUT, 24,
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self.div_read, self.chip_select)
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delay(270*ns) # t_21 min sync high in readback
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self.bus.write((AD53XX_CMD_SPECIAL | AD53XX_SPECIAL_NOP) << 8)
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self.bus.set_config_mu(SPI_AD53XX_CONFIG, 24, self.div_write,
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self.chip_select)
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return self.bus.read()
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@kernel
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def write_offset_dacs_mu(self, value):
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"""Program the OFS0 and OFS1 offset DAC registers.
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Writes to the offset DACs take effect immediately without requiring
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a LDAC. This method advances the timeline by the duration of two SPI
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transfers.
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:param value: Value to set both offset DAC registers to
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"""
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value &= 0x3fff
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self.offset_dacs = value
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self.bus.write((AD53XX_CMD_SPECIAL | AD53XX_SPECIAL_OFS0 | value) << 8)
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self.bus.write((AD53XX_CMD_SPECIAL | AD53XX_SPECIAL_OFS1 | value) << 8)
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@kernel
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def write_gain_mu(self, channel, gain=0xffff):
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"""Program the gain register for a DAC channel.
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The DAC output is not updated until LDAC is pulsed (see :meth load:).
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This method advances the timeline by the duration of one SPI transfer.
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:param gain: 16-bit gain register value (default: 0xffff)
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"""
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self.bus.write(ad53xx_cmd_write_ch(channel, gain, AD53XX_CMD_GAIN))
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@kernel
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def write_offset_mu(self, channel, offset=0x8000):
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"""Program the offset register for a DAC channel.
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The DAC output is not updated until LDAC is pulsed (see :meth load:).
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This method advances the timeline by the duration of one SPI transfer.
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:param offset: 16-bit offset register value (default: 0x8000)
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"""
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self.bus.write(ad53xx_cmd_write_ch(channel, offset, AD53XX_CMD_OFFSET))
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@kernel
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def write_offset(self, channel, voltage):
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"""Program the DAC offset voltage for a channel.
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An offset of +V can be used to trim out a DAC offset error of -V.
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The DAC output is not updated until LDAC is pulsed (see :meth load:).
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This method advances the timeline by the duration of one SPI transfer.
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:param voltage: the offset voltage
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"""
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self.write_offset_mu(channel, offset_to_mu(voltage, self.offset_dacs,
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self.vref))
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@kernel
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def write_dac_mu(self, channel, value):
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"""Program the DAC input register for a channel.
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||||
The DAC output is not updated until LDAC is pulsed (see :meth load:).
|
||||
This method advances the timeline by the duration of one SPI transfer.
|
||||
"""
|
||||
self.bus.write(ad53xx_cmd_write_ch(channel, value, AD53XX_CMD_DATA))
|
||||
|
||||
@kernel
|
||||
def write_dac(self, channel, voltage):
|
||||
"""Program the DAC output voltage for a channel.
|
||||
|
||||
The DAC output is not updated until LDAC is pulsed (see :meth load:).
|
||||
This method advances the timeline by the duration of one SPI transfer.
|
||||
"""
|
||||
self.write_dac_mu(channel, voltage_to_mu(voltage, self.offset_dacs,
|
||||
self.vref))
|
||||
|
||||
@kernel
|
||||
def load(self):
|
||||
"""Pulse the LDAC line.
|
||||
|
||||
Note that there is a <= 1.5us "BUSY" period (t10) after writing to a
|
||||
DAC input/gain/offset register. All DAC registers may be programmed
|
||||
normally during the busy period, however LDACs during the busy period
|
||||
cause the DAC output to change *after* the BUSY period has completed,
|
||||
instead of the usual immediate update on LDAC behaviour.
|
||||
|
||||
This method advances the timeline by two RTIO clock periods.
|
||||
"""
|
||||
self.ldac.off()
|
||||
delay_mu(2*self.bus.ref_period_mu) # t13 = 10ns ldac pulse width low
|
||||
self.ldac.on()
|
||||
|
||||
@kernel
|
||||
def set_dac_mu(self, values, channels=list(range(40))):
|
||||
"""Program multiple DAC channels and pulse LDAC to update the DAC
|
||||
outputs.
|
||||
|
||||
This method does not advance the timeline; write events are scheduled
|
||||
in the past. The DACs will synchronously start changing their output
|
||||
levels `now`.
|
||||
|
||||
See :meth load:.
|
||||
|
||||
:param values: list of DAC values to program
|
||||
:param channels: list of DAC channels to program. If not specified,
|
||||
we program the DAC channels sequentially, starting at 0.
|
||||
"""
|
||||
t0 = now_mu()
|
||||
|
||||
# t10: max busy period after writing to DAC registers
|
||||
t_10 = self.core.seconds_to_mu(1500*ns)
|
||||
# compensate all delays that will be applied
|
||||
delay_mu(-t_10-len(values)*self.bus.xfer_duration_mu)
|
||||
for i in range(len(values)):
|
||||
self.write_dac_mu(channels[i], values[i])
|
||||
delay_mu(t_10)
|
||||
self.load()
|
||||
at_mu(t0)
|
||||
|
||||
@kernel
|
||||
def set_dac(self, voltages, channels=list(range(40))):
|
||||
"""Program multiple DAC channels and pulse LDAC to update the DAC
|
||||
outputs.
|
||||
|
||||
This method does not advance the timeline; write events are scheduled
|
||||
in the past. The DACs will synchronously start changing their output
|
||||
levels `now`.
|
||||
|
||||
:param voltages: list of voltages to program the DAC channels to
|
||||
:param channels: list of DAC channels to program. If not specified,
|
||||
we program the DAC channels sequentially, starting at 0.
|
||||
"""
|
||||
values = [voltage_to_mu(voltage, self.offset_dacs, self.vref)
|
||||
for voltage in voltages]
|
||||
self.set_dac_mu(values, channels)
|
||||
|
||||
@kernel
|
||||
def calibrate(self, channel, vzs, vfs):
|
||||
""" Two-point calibration of a DAC channel.
|
||||
|
||||
Programs the offset and gain register to trim out DAC errors. Does not
|
||||
take effect until LDAC is pulsed (see :meth load:).
|
||||
|
||||
Calibration consists of measuring the DAC output voltage for a channel
|
||||
with the DAC set to zero-scale (0x0000) and full-scale (0xffff).
|
||||
|
||||
Note that only negative offsets and full-scale errors (DAC gain too
|
||||
high) can be calibrated in this fashion.
|
||||
|
||||
:param channel: The number of the calibrated channel
|
||||
:params vzs: Measured voltage with the DAC set to zero-scale (0x0000)
|
||||
:params vfs: Measured voltage with the DAC set to full-scale (0xffff)
|
||||
"""
|
||||
offset_err = voltage_to_mu(vzs, self.offset_dacs, self.vref)
|
||||
gain_err = voltage_to_mu(vfs, self.offset_dacs, self.vref) - (
|
||||
offset_err + 0xffff)
|
||||
|
||||
assert offset_err <= 0
|
||||
assert gain_err >= 0
|
||||
|
||||
self.core.break_realtime()
|
||||
self.write_offset_mu(channel, 0x8000-offset_err)
|
||||
self.write_gain_mu(channel, 0xffff-gain_err)
|
||||
53
artiq/coredevice/zotino.py
Normal file
53
artiq/coredevice/zotino.py
Normal file
@ -0,0 +1,53 @@
|
||||
"""RTIO driver for the Zotino 32-channel, 16-bit 1MSPS DAC.
|
||||
|
||||
Output event replacement is not supported and issuing commands at the same
|
||||
time is an error.
|
||||
"""
|
||||
|
||||
from artiq.language.core import kernel
|
||||
from artiq.coredevice import spi2 as spi
|
||||
from artiq.coredevice.ad53xx import SPI_AD53XX_CONFIG, AD53xx
|
||||
|
||||
_SPI_DAC_CONFIG = SPI_AD53XX_CONFIG
|
||||
_SPI_SR_CONFIG = (0*spi.SPI_OFFLINE | 1*spi.SPI_END |
|
||||
0*spi.SPI_INPUT | 0*spi.SPI_CS_POLARITY |
|
||||
0*spi.SPI_CLK_POLARITY | 0*spi.SPI_CLK_PHASE |
|
||||
0*spi.SPI_LSB_FIRST | 0*spi.SPI_HALF_DUPLEX)
|
||||
|
||||
_SPI_CS_DAC = 1
|
||||
_SPI_CS_SR = 2
|
||||
|
||||
class Zotino(AD53xx):
|
||||
""" Zotino 32-channel, 16-bit 1MSPS DAC.
|
||||
|
||||
Controls the AD5372 DAC and the 8 user LEDs via a shared SPI interface.
|
||||
|
||||
:param spi_device: SPI bus device name
|
||||
:param ldac_device: LDAC RTIO TTLOut channel name.
|
||||
:param clr_device: CLR RTIO TTLOut channel name.
|
||||
:param div_write: SPI clock divider for write operations (default: 4,
|
||||
50MHz max SPI clock)
|
||||
:param div_read: SPI clock divider for read operations (default: 8, not
|
||||
optimized for speed, but cf data sheet t22: 25ns min SCLK edge to SDO
|
||||
valid)
|
||||
:param vref: DAC reference voltage (default: 5.)
|
||||
:param core_device: Core device name (default: "core")
|
||||
"""
|
||||
|
||||
def __init__(self, dmgr, spi_device, ldac_device, clr_device,
|
||||
div_write=4, div_read=8, vref=5., core="core"):
|
||||
AD53xx.__init__(self, dmgr=dmgr, spi_device=spi_device,
|
||||
ldac_device=ldac_device, clr_device=clr_device,
|
||||
chip_select=_SPI_CS_DAC, div_write=div_write,
|
||||
div_read=div_read, core=core)
|
||||
|
||||
@ kernel
|
||||
def set_leds(self, leds):
|
||||
""" Sets the states of the 8 user LEDs.
|
||||
|
||||
:param leds: 8-bit word with LED state
|
||||
"""
|
||||
self.bus.set_config_mu(_SPI_SR_CONFIG, 8, self.div_write, _SPI_CS_SR)
|
||||
self.bus.write(leds << 24)
|
||||
self.bus.set_config_mu(_SPI_DAC_CONFIG, 24, self.div_write,
|
||||
_SPI_CS_DAC)
|
||||
@ -198,15 +198,6 @@ device_db = {
|
||||
"class": "TTLOut",
|
||||
"arguments": {"channel": 25}
|
||||
},
|
||||
"novogorny0" : {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.novogorny",
|
||||
"class": "Novogorny",
|
||||
"arguments": {
|
||||
"spi_device": "spi_novogorny0",
|
||||
"cnv_device": "ttl_novogorny0_cnv",
|
||||
}
|
||||
},
|
||||
|
||||
"spi_urukul0": {
|
||||
"type": "local",
|
||||
@ -311,5 +302,34 @@ device_db = {
|
||||
"module": "artiq.coredevice.ttl",
|
||||
"class": "TTLOut",
|
||||
"arguments": {"channel": 33}
|
||||
},
|
||||
|
||||
"spi_zotino0": {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.spi2",
|
||||
"class": "SPIMaster",
|
||||
"arguments": {"channel": 36}
|
||||
},
|
||||
"ttl_zotino0_ldac": {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.ttl",
|
||||
"class": "TTLOut",
|
||||
"arguments": {"channel": 37}
|
||||
},
|
||||
"ttl_zotino0_clr": {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.ttl",
|
||||
"class": "TTLOut",
|
||||
"arguments": {"channel": 38}
|
||||
},
|
||||
"zotino0": {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.zotino",
|
||||
"class": "Zotino",
|
||||
"arguments": {
|
||||
"spi_device": "spi_zotino0",
|
||||
"ldac_device": "ttl_zotino0_ldac",
|
||||
"clr_device": "ttl_zotino0_clr"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user