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gateware/spi: style

This commit is contained in:
Sebastien Bourdeauducq 2017-10-23 18:45:53 +08:00
parent a6b45caefa
commit a9798ae2b1
2 changed files with 3 additions and 3 deletions
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4
artiq/coredevice/ad5360.py
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@ -174,8 +174,8 @@ class AD5360:
self.bus.ref_period_mu) - self.bus.ref_period_mu) -
3*self.bus.ref_period_mu - 3*self.bus.ref_period_mu -
self.core.seconds_to_mu(1.5*us)) self.core.seconds_to_mu(1.5*us))
for i in range(len(values)): for i, value in enumerate(values):
self.write_channel(i, values[i], op) self.write_channel(i, value, op)
delay_mu(3*self.bus.ref_period_mu + # latency alignment ttl to spi delay_mu(3*self.bus.ref_period_mu + # latency alignment ttl to spi
self.core.seconds_to_mu(1.5*us)) # t10 max busy low for one channel self.core.seconds_to_mu(1.5*us)) # t10 max busy low for one channel
self.load() self.load()

2
artiq/coredevice/spi.py
View File

@ -15,7 +15,7 @@ from artiq.coredevice.rtio import rtio_output, rtio_input_data
__all__ = [ __all__ = [
"SPI_DATA_ADDR", "SPI_XFER_ADDR", "SPI_CONFIG_ADDR", "SPI_DATA_ADDR", "SPI_XFER_ADDR", "SPI_CONFIG_ADDR",
"SPI_OFFLINE", "SPI_ACTIVE", "SPI_PENDING", "SPI_OFFLINE", "SPI_ACTIVE", "SPI_PENDING",
"SPI_CS_POLARITY", "SPI_CLK_POLARITY", "SPI_CLK_PHASE", "SPI_CS_POLARITY", "SPI_CLK_POLARITY", "SPI_CLK_PHASE",
"SPI_LSB_FIRST", "SPI_HALF_DUPLEX", "SPI_LSB_FIRST", "SPI_HALF_DUPLEX",