From a8b211f8912b878f1ae5346430113e44b7375bbe Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Wed, 15 Jun 2016 15:04:04 +0200 Subject: [PATCH] spi: cross-reference bit ordering and alignment, closes #482 --- artiq/coredevice/spi.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/artiq/coredevice/spi.py b/artiq/coredevice/spi.py index 80909e527..a67539100 100644 --- a/artiq/coredevice/spi.py +++ b/artiq/coredevice/spi.py @@ -196,6 +196,7 @@ class SPIMaster: deasserting ``cs`` in between. Once a transfer completes, the previous transfer's read data is available in the ``data`` register. + * For bit alignment and bit ordering see :meth:`set_config`. This method advances the timeline by the duration of the SPI transfer. If a transfer is to be chained, the timeline needs to be rewound. @@ -207,6 +208,8 @@ class SPIMaster: def read_async(self): """Trigger an asynchronous read from the ``data`` register. + For bit alignment and bit ordering see :meth:`set_config`. + Reads always finish in two cycles. Every data register read triggered by a :meth:`read_async`