M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

runtime: tune Sayma SYSREF phases

This commit is contained in:
Sebastien Bourdeauducq 2018-06-27 17:31:29 +08:00
parent e9a1e10221
commit a8a2ad68d3
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
artiq/firmware/runtime/main.rs
View File

@ -57,9 +57,9 @@ mod moninj;
mod analyzer;
#[cfg(has_ad9154)]
const SYSREF_PHASE_FPGA: u16 = 20;
const SYSREF_PHASE_FPGA: u16 = 35;
#[cfg(has_ad9154)]
const SYSREF_PHASE_DAC: u16 = 31;
const SYSREF_PHASE_DAC: u16 = 64;
fn startup() {
irq::set_mask(0);