mirror of https://github.com/m-labs/artiq.git
artiq_run: port to NAC3 (WIP)
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df87cc88d6
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@ -14,11 +14,8 @@ from sipyco import common_args
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from artiq import __version__ as artiq_version
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from artiq import __version__ as artiq_version
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from artiq.language.environment import EnvExperiment, ProcessArgumentManager
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from artiq.language.environment import EnvExperiment, ProcessArgumentManager
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from artiq.language.types import TBool
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from artiq.master.databases import DeviceDB, DatasetDB
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from artiq.master.databases import DeviceDB, DatasetDB
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from artiq.master.worker_db import DeviceManager, DatasetManager
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from artiq.master.worker_db import DeviceManager, DatasetManager
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from artiq.coredevice.core import CompileError, host_only
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from artiq.compiler.embedding import EmbeddingMap
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from artiq.compiler import import_cache
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from artiq.compiler import import_cache
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from artiq.tools import *
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from artiq.tools import *
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@ -92,10 +89,9 @@ class DummyScheduler:
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def get_status(self):
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def get_status(self):
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return dict()
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return dict()
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def check_pause(self, rid=None) -> TBool:
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def check_pause(self, rid=None) -> bool:
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return False
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return False
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@host_only
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def pause(self):
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def pause(self):
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pass
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pass
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@ -178,8 +174,6 @@ def run(with_file=False):
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exp_inst.prepare()
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exp_inst.prepare()
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exp_inst.run()
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exp_inst.run()
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exp_inst.analyze()
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exp_inst.analyze()
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except CompileError as error:
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return
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except Exception as exn:
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except Exception as exn:
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if hasattr(exn, "artiq_core_exception"):
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if hasattr(exn, "artiq_core_exception"):
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print(exn.artiq_core_exception, file=sys.stderr)
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print(exn.artiq_core_exception, file=sys.stderr)
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