From a7de58b6044db4e262f74030b4a41ee536f82c99 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 14 Mar 2017 14:18:55 +0800 Subject: [PATCH] =?UTF-8?q?rtio:=20Inout=20=E2=86=92=20InOut?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- artiq/gateware/rtio/phy/ttl_serdes_7series.py | 8 ++++---- artiq/gateware/rtio/phy/ttl_serdes_generic.py | 8 ++++---- artiq/gateware/rtio/phy/ttl_serdes_spartan6.py | 8 ++++---- artiq/gateware/rtio/phy/ttl_simple.py | 2 +- artiq/gateware/targets/kc705_dds.py | 10 +++++----- artiq/gateware/targets/kc705_drtio_master.py | 2 +- artiq/gateware/targets/kc705_drtio_satellite.py | 2 +- artiq/gateware/targets/phaser.py | 2 +- artiq/gateware/targets/pipistrello.py | 2 +- 9 files changed, 22 insertions(+), 22 deletions(-) diff --git a/artiq/gateware/rtio/phy/ttl_serdes_7series.py b/artiq/gateware/rtio/phy/ttl_serdes_7series.py index e1d5278f5..266037e1e 100644 --- a/artiq/gateware/rtio/phy/ttl_serdes_7series.py +++ b/artiq/gateware/rtio/phy/ttl_serdes_7series.py @@ -101,15 +101,15 @@ class Output_8X(ttl_serdes_generic.Output): ttl_serdes_generic.Output.__init__(self, serdes) -class Inout_8X(ttl_serdes_generic.Inout): +class InOut_8X(ttl_serdes_generic.InOut): def __init__(self, pad, pad_n=None): serdes = _IOSERDESE2_8X(pad, pad_n) self.submodules += serdes - ttl_serdes_generic.Inout.__init__(self, serdes) + ttl_serdes_generic.InOut.__init__(self, serdes) -class Input_8X(ttl_serdes_generic.Inout): +class Input_8X(ttl_serdes_generic.InOut): def __init__(self, pad, pad_n=None): serdes = _ISERDESE2_8X(pad, pad_n) self.submodules += serdes - ttl_serdes_generic.Inout.__init__(self, serdes) + ttl_serdes_generic.InOut.__init__(self, serdes) diff --git a/artiq/gateware/rtio/phy/ttl_serdes_generic.py b/artiq/gateware/rtio/phy/ttl_serdes_generic.py index 06bf186fc..0d88c4284 100644 --- a/artiq/gateware/rtio/phy/ttl_serdes_generic.py +++ b/artiq/gateware/rtio/phy/ttl_serdes_generic.py @@ -54,7 +54,7 @@ class Output(Module): override_en, override_o) -class Inout(Module): +class InOut(Module): def __init__(self, serdes): serdes_width = len(serdes.o) assert len(serdes.i) == serdes_width @@ -150,10 +150,10 @@ class _OutputTB(Module): yield -class _InoutTB(Module): +class _InOutTB(Module): def __init__(self): self.serdes = _FakeSerdes() - self.submodules.dut = RenameClockDomains(Inout(self.serdes), + self.submodules.dut = RenameClockDomains(InOut(self.serdes), {"rio_phy": "sys", "rio": "sys"}) @@ -273,7 +273,7 @@ if __name__ == "__main__": cls = { "output": _OutputTB, - "inout": _InoutTB + "inout": _InOutTB }[sys.argv[1]] with Simulator(cls(), TopLevel("top.vcd", clk_period=int(1/0.125))) as s: diff --git a/artiq/gateware/rtio/phy/ttl_serdes_spartan6.py b/artiq/gateware/rtio/phy/ttl_serdes_spartan6.py index bf851a662..1a772f3f8 100644 --- a/artiq/gateware/rtio/phy/ttl_serdes_spartan6.py +++ b/artiq/gateware/rtio/phy/ttl_serdes_spartan6.py @@ -84,11 +84,11 @@ class Output_8X(ttl_serdes_generic.Output): ttl_serdes_generic.Output.__init__(self, serdes) -class Inout_8X(ttl_serdes_generic.Inout): +class InOut_8X(ttl_serdes_generic.InOut): def __init__(self, pad, stb): serdes = _IOSERDES2_8X(pad, stb) self.submodules += serdes - ttl_serdes_generic.Inout.__init__(self, serdes) + ttl_serdes_generic.InOut.__init__(self, serdes) class _OSERDES2_4X(Module): @@ -149,8 +149,8 @@ class Output_4X(ttl_serdes_generic.Output): ttl_serdes_generic.Output.__init__(self, serdes) -class Inout_4X(ttl_serdes_generic.Inout): +class InOut_4X(ttl_serdes_generic.InOut): def __init__(self, pad, stb): serdes = _IOSERDES2_4X(pad, stb) self.submodules += serdes - ttl_serdes_generic.Inout.__init__(self, serdes) + ttl_serdes_generic.InOut.__init__(self, serdes) diff --git a/artiq/gateware/rtio/phy/ttl_simple.py b/artiq/gateware/rtio/phy/ttl_simple.py index 85c03af6d..d5129606a 100644 --- a/artiq/gateware/rtio/phy/ttl_simple.py +++ b/artiq/gateware/rtio/phy/ttl_simple.py @@ -64,7 +64,7 @@ class Input(Module): self.probes += [i] -class Inout(Module): +class InOut(Module): def __init__(self, pad): self.rtlink = rtlink.Interface( rtlink.OInterface(2, 2), diff --git a/artiq/gateware/targets/kc705_dds.py b/artiq/gateware/targets/kc705_dds.py index f154daaee..4ecb108e1 100755 --- a/artiq/gateware/targets/kc705_dds.py +++ b/artiq/gateware/targets/kc705_dds.py @@ -177,7 +177,7 @@ class NIST_CLOCK(_NIST_Ions): rtio_channels = [] for i in range(16): if i % 4 == 3: - phy = ttl_serdes_7series.Inout_8X(platform.request("ttl", i)) + phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) else: @@ -186,11 +186,11 @@ class NIST_CLOCK(_NIST_Ions): rtio_channels.append(rtio.Channel.from_phy(phy)) for i in range(2): - phy = ttl_serdes_7series.Inout_8X(platform.request("pmt", i)) + phy = ttl_serdes_7series.InOut_8X(platform.request("pmt", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) - phy = ttl_serdes_7series.Inout_8X(platform.request("user_sma_gpio_n_33")) + phy = ttl_serdes_7series.InOut_8X(platform.request("user_sma_gpio_n_33")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) @@ -247,7 +247,7 @@ class NIST_QC2(_NIST_Ions): # All TTL channels are In+Out capable for i in range(40): - phy = ttl_serdes_7series.Inout_8X( + phy = ttl_serdes_7series.InOut_8X( platform.request("ttl", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) @@ -260,7 +260,7 @@ class NIST_QC2(_NIST_Ions): clock_generators.append(rtio.Channel.from_phy(phy)) # user SMA on KC705 board - phy = ttl_serdes_7series.Inout_8X(platform.request("user_sma_gpio_n_33")) + phy = ttl_serdes_7series.InOut_8X(platform.request("user_sma_gpio_n_33")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) diff --git a/artiq/gateware/targets/kc705_drtio_master.py b/artiq/gateware/targets/kc705_drtio_master.py index 9e16ead4e..150676460 100755 --- a/artiq/gateware/targets/kc705_drtio_master.py +++ b/artiq/gateware/targets/kc705_drtio_master.py @@ -96,7 +96,7 @@ class Master(MiniSoC, AMPSoC): self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) for sma in "user_sma_gpio_p", "user_sma_gpio_n": - phy = ttl_simple.Inout(platform.request(sma)) + phy = ttl_simple.InOut(platform.request(sma)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) diff --git a/artiq/gateware/targets/kc705_drtio_satellite.py b/artiq/gateware/targets/kc705_drtio_satellite.py index b7c26f68f..59b3d1940 100755 --- a/artiq/gateware/targets/kc705_drtio_satellite.py +++ b/artiq/gateware/targets/kc705_drtio_satellite.py @@ -40,7 +40,7 @@ class Satellite(BaseSoC): self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) for sma in "user_sma_gpio_p", "user_sma_gpio_n": - phy = ttl_simple.Inout(platform.request(sma)) + phy = ttl_simple.InOut(platform.request(sma)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) diff --git a/artiq/gateware/targets/phaser.py b/artiq/gateware/targets/phaser.py index e897d82e4..56d6fdaa5 100755 --- a/artiq/gateware/targets/phaser.py +++ b/artiq/gateware/targets/phaser.py @@ -203,7 +203,7 @@ class Phaser(MiniSoC, AMPSoC): rtio_channels = [] - phy = ttl_serdes_7series.Inout_8X( + phy = ttl_serdes_7series.InOut_8X( platform.request("user_sma_gpio_n")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128)) diff --git a/artiq/gateware/targets/pipistrello.py b/artiq/gateware/targets/pipistrello.py index 8f3d80a28..86721bd20 100755 --- a/artiq/gateware/targets/pipistrello.py +++ b/artiq/gateware/targets/pipistrello.py @@ -182,7 +182,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd # the last TTL is used for ClockGen for i in range(15): if i in (0, 1): - phy = ttl_serdes_spartan6.Inout_4X(platform.request("ttl", i), + phy = ttl_serdes_spartan6.InOut_4X(platform.request("ttl", i), self.rtio_crg.rtiox4_stb) elif i in (2,): phy = ttl_serdes_spartan6.Output_8X(platform.request("ttl", i),