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almazny: fix minor doc formatting

This commit is contained in:
Florian Agbuya 2023-09-06 14:05:41 +08:00 committed by Sébastien Bourdeauducq
parent 0188f31f3a
commit a619c9f3c2
1 changed files with 8 additions and 7 deletions
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15
artiq/coredevice/almazny.py
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@ -62,9 +62,9 @@ class AlmaznyLegacy:
"""
Sets attenuators on chosen shift register (channel).
:param channel - index of the register [0-3]
:param att - attenuation setting in dBm [0-31.5]
:param rf_switch - rf switch (bool)
:param channel: index of the register [0-3]
:param att: attenuation setting in dBm [0-31.5]
:param rf_switch: rf switch (bool)
"""
self.set_att_mu(channel, self.att_to_mu(att), rf_switch)
@ -73,9 +73,9 @@ class AlmaznyLegacy:
"""
Sets attenuators on chosen shift register (channel).
:param channel - index of the register [0-3]
:param att_mu - attenuation setting in machine units [0-63]
:param rf_switch - rf switch (bool)
:param channel: index of the register [0-3]
:param att_mu: attenuation setting in machine units [0-63]
:param rf_switch: rf switch (bool)
"""
self.channel_sw[channel] = 1 if rf_switch else 0
self.att_mu[channel] = att_mu
@ -86,7 +86,7 @@ class AlmaznyLegacy:
"""
Toggles output on all shift registers on or off.
:param oe - toggle output enable (bool)
:param oe: toggle output enable (bool)
"""
self.output_enable = oe
cfg_reg = self.mirny_cpld.read_reg(1)
@ -131,6 +131,7 @@ class AlmaznyChannel:
This driver requires Almazny hardware revision v1.2 or later
and Mirny CPLD gateware v0.3 or later.
Use :class:`artiq.coredevice.almazny.AlmaznyLegacy` for Almazny hardware v1.1 and earlier.
:param host_mirny: Mirny CPLD device name
:param channel: channel index (0-3)
"""