M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-29 21:23:34 +08:00
Code Issues Projects Releases Wiki Activity

rtio: SED, InputCollector use rio clock domain

Browse Source
This commit is contained in:
mwojcik 2023-04-28 14:49:55 +08:00 committed by Sébastien Bourdeauducq
parent 0bf57f4ebd
commit a533f2a0cd
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
artiq/gateware/rtio/core.py
View File

@ -60,17 +60,17 @@ class Core(Module, AutoCSR):
# Outputs/Inputs
quash_channels = [n for n, c in enumerate(channels) if isinstance(c, LogChannel)]
outputs = SED(channels, tsc.glbl_fine_ts_width,
outputs = ClockDomainsRenamer("rio")(SED(channels, tsc.glbl_fine_ts_width,
quash_channels=quash_channels,
lane_count=lane_count, fifo_depth=fifo_depth,
interface=self.cri)
interface=self.cri))
self.submodules += outputs
self.comb += outputs.coarse_timestamp.eq(tsc.coarse_ts)
self.sync += outputs.minimum_coarse_timestamp.eq(tsc.coarse_ts + 12)
inputs = InputCollector(tsc, channels,
inputs = ClockDomainsRenamer("rio")(InputCollector(tsc, channels,
quash_channels=quash_channels,
interface=self.cri)
interface=self.cri))
self.submodules += inputs
# Asychronous output errors