mirror of https://github.com/m-labs/artiq.git
urukul: expose PROFILE setting
* add documentation * add unittest Signed-off-by: Robert Jördens <rj@quartiq.de>
This commit is contained in:
parent
2af6edb8f5
commit
a52d1be140
|
@ -335,3 +335,15 @@ class CPLD:
|
||||||
ftw = ftw_max//div
|
ftw = ftw_max//div
|
||||||
assert ftw*div == ftw_max
|
assert ftw*div == ftw_max
|
||||||
self.sync.set_mu(ftw)
|
self.sync.set_mu(ftw)
|
||||||
|
|
||||||
|
@kernel
|
||||||
|
def set_profile(self, profile):
|
||||||
|
"""Set the PROFILE pins.
|
||||||
|
|
||||||
|
The PROFILE pins are common to all four DDS channels.
|
||||||
|
|
||||||
|
:param profile: PROFILE pins in numeric representation (0-7).
|
||||||
|
"""
|
||||||
|
cfg = self.cfg_reg & ~(7 << CFG_PROFILE)
|
||||||
|
cfg |= (profile & 7) << CFG_PROFILE
|
||||||
|
self.cfg_write(cfg)
|
||||||
|
|
|
@ -98,6 +98,13 @@ class UrukulExp(EnvExperiment):
|
||||||
self.dev.init()
|
self.dev.init()
|
||||||
self.dev.set_sync_div(2)
|
self.dev.set_sync_div(2)
|
||||||
|
|
||||||
|
@kernel
|
||||||
|
def profile(self):
|
||||||
|
self.core.break_realtime()
|
||||||
|
self.dev.init()
|
||||||
|
self.dev.set_profile(7)
|
||||||
|
self.dev.set_profile(0)
|
||||||
|
|
||||||
|
|
||||||
class UrukulTest(ExperimentCase):
|
class UrukulTest(ExperimentCase):
|
||||||
def test_instantiate(self):
|
def test_instantiate(self):
|
||||||
|
@ -147,3 +154,6 @@ class UrukulTest(ExperimentCase):
|
||||||
|
|
||||||
def test_sync(self):
|
def test_sync(self):
|
||||||
self.execute(UrukulExp, "sync")
|
self.execute(UrukulExp, "sync")
|
||||||
|
|
||||||
|
def test_profile(self):
|
||||||
|
self.execute(UrukulExp, "profile")
|
||||||
|
|
Loading…
Reference in New Issue