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drtio: more simple fixes

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This commit is contained in:
Sebastien Bourdeauducq 2016-10-24 23:32:49 +08:00
parent 029e0d95b7
commit a4e85081aa
2 changed files with 4 additions and 3 deletions
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4
artiq/gateware/drtio/core.py
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@ -38,9 +38,9 @@ class DRTIOSatellite(Module):
self.clock_domains.cd_rio_phy = ClockDomain() self.clock_domains.cd_rio_phy = ClockDomain()
self.comb += [ self.comb += [
self.cd_rio.clk.eq(ClockSignal("rtio")), self.cd_rio.clk.eq(ClockSignal("rtio")),
self.cd_rio.rst.eq(ResetSignal("rtio")), self.cd_rio.rst.eq(ResetSignal("rtio", allow_reset_less=True)),
self.cd_rio_phy.clk.eq(ClockSignal("rtio")), self.cd_rio_phy.clk.eq(ClockSignal("rtio")),
self.cd_rio_phy.rst.eq(ResetSignal("rtio")), self.cd_rio_phy.rst.eq(ResetSignal("rtio", allow_reset_less=True)),
] ]

3
artiq/gateware/drtio/rt_packets.py
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@ -406,7 +406,8 @@ class RTPacketMaster(Module):
# # # # # #
# CDC # CDC
wfifo = AsyncFIFO(64+16+16+256, write_fifo_depth) wfifo = ClockDomainsRenamer({"write": "sys", "read": "rtio"})(
AsyncFIFO(64+16+16+256, write_fifo_depth))
self.submodules += wfifo self.submodules += wfifo
write_timestamp = Signal(64) write_timestamp = Signal(64)
write_channel = Signal(16) write_channel = Signal(16)