diff --git a/artiq/gateware/drtio/core.py b/artiq/gateware/drtio/core.py
index 7fcfb7110..95260f773 100644
--- a/artiq/gateware/drtio/core.py
+++ b/artiq/gateware/drtio/core.py
@@ -38,9 +38,9 @@ class DRTIOSatellite(Module):
         self.clock_domains.cd_rio_phy = ClockDomain()
         self.comb += [
             self.cd_rio.clk.eq(ClockSignal("rtio")),
-            self.cd_rio.rst.eq(ResetSignal("rtio")),
+            self.cd_rio.rst.eq(ResetSignal("rtio", allow_reset_less=True)),
             self.cd_rio_phy.clk.eq(ClockSignal("rtio")),
-            self.cd_rio_phy.rst.eq(ResetSignal("rtio")),
+            self.cd_rio_phy.rst.eq(ResetSignal("rtio", allow_reset_less=True)),
         ]
 
 
diff --git a/artiq/gateware/drtio/rt_packets.py b/artiq/gateware/drtio/rt_packets.py
index 1f0dc6039..51ad16368 100644
--- a/artiq/gateware/drtio/rt_packets.py
+++ b/artiq/gateware/drtio/rt_packets.py
@@ -406,7 +406,8 @@ class RTPacketMaster(Module):
         # # #
 
         # CDC
-        wfifo = AsyncFIFO(64+16+16+256, write_fifo_depth)
+        wfifo = ClockDomainsRenamer({"write": "sys", "read": "rtio"})(
+            AsyncFIFO(64+16+16+256, write_fifo_depth))
         self.submodules += wfifo
         write_timestamp = Signal(64)
         write_channel = Signal(16)