mirror of https://github.com/m-labs/artiq.git
fastino: port to NAC3
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@ -3,13 +3,23 @@ streaming DAC.
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"""
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from numpy import int32, int64
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from artiq.language.core import kernel, portable, delay, delay_mu
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from artiq.language.core import nac3, kernel, portable, KernelInvariant
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from artiq.coredevice.rtio import (rtio_output, rtio_output_wide,
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rtio_input_data)
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from artiq.language.units import ns
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from artiq.language.types import TInt32, TList
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from artiq.coredevice.core import Core
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# NAC3TODO work around https://git.m-labs.hk/M-Labs/nac3/issues/189
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@nac3
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class ValueError(Exception):
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pass
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@nac3
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class NotImplementedError(Exception):
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pass
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@nac3
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class Fastino:
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"""Fastino 32-channel, 16-bit, 2.5 MS/s per channel streaming DAC
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@ -41,7 +51,11 @@ class Fastino:
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:param log2_width: Width of DAC channel group (logarithm base 2).
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Value must match the corresponding value in the RTIO PHY (gateware).
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"""
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kernel_invariants = {"core", "channel", "width", "t_frame"}
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core: KernelInvariant[Core]
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channel: KernelInvariant[int32]
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width: KernelInvariant[int32]
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t_frame: KernelInvariant[int64]
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def __init__(self, dmgr, channel, core_device="core", log2_width=0):
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self.channel = channel << 8
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@ -69,15 +83,15 @@ class Fastino:
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Note: On Fastino gateware before v0.2 this may lead to 0 voltage being emitted
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transiently.
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"""
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self.set_cfg(reset=0, afe_power_down=0, dac_clr=0, clr_err=1)
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self.set_cfg(reset=False, afe_power_down=False, dac_clr=False, clr_err=True)
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delay_mu(self.t_frame)
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self.set_cfg(reset=0, afe_power_down=0, dac_clr=0, clr_err=0)
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self.set_cfg(reset=False, afe_power_down=False, dac_clr=False, clr_err=False)
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delay_mu(self.t_frame)
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self.set_continuous(0)
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delay_mu(self.t_frame)
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self.stage_cic(1)
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delay_mu(self.t_frame)
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self.apply_cic(0xffffffff)
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self.apply_cic(int32(int64(0xffffffff)))
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delay_mu(self.t_frame)
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self.set_leds(0)
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delay_mu(self.t_frame)
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@ -85,7 +99,7 @@ class Fastino:
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delay_mu(self.t_frame)
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@kernel
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def write(self, addr, data):
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def write(self, addr: int32, data: int32):
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"""Write data to a Fastino register.
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:param addr: Address to write to.
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@ -94,7 +108,7 @@ class Fastino:
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rtio_output(self.channel | addr, data)
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@kernel
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def read(self, addr):
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def read(self, addr: int32):
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"""Read from Fastino register.
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TODO: untested
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@ -102,12 +116,12 @@ class Fastino:
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:param addr: Address to read from.
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:return: The data read.
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"""
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raise NotImplementedError
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raise NotImplementedError()
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# rtio_output(self.channel | addr | 0x80)
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# return rtio_input_data(self.channel >> 8)
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@kernel
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def set_dac_mu(self, dac, data):
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def set_dac_mu(self, dac: int32, data: int32):
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"""Write DAC data in machine units.
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:param dac: DAC channel to write to (0-31).
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@ -117,7 +131,7 @@ class Fastino:
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self.write(dac, data)
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@kernel
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def set_group_mu(self, dac: TInt32, data: TList(TInt32)):
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def set_group_mu(self, dac: int32, data: list[int32]):
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"""Write a group of DAC channels in machine units.
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:param dac: First channel in DAC channel group (0-31). The `log2_width`
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@ -127,24 +141,24 @@ class Fastino:
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If the list length is less than group size, the remaining
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DAC channels within the group are cleared to 0 (machine units).
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"""
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if dac & (self.width - 1):
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if dac & (self.width - 1) != 0:
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raise ValueError("Group index LSBs must be zero")
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rtio_output_wide(self.channel | dac, data)
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@portable
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def voltage_to_mu(self, voltage):
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def voltage_to_mu(self, voltage: float) -> int32:
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"""Convert SI Volts to DAC machine units.
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:param voltage: Voltage in SI Volts.
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:return: DAC data word in machine units, 16 bit integer.
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"""
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data = int32(round((0x8000/10.)*voltage)) + int32(0x8000)
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data = int32(round((float(0x8000)/10.)*voltage)) + int32(0x8000)
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if data < 0 or data > 0xffff:
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raise ValueError("DAC voltage out of bounds")
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return data
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@portable
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def voltage_group_to_mu(self, voltage, data):
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def voltage_group_to_mu(self, voltage: list[float], data: list[int32]):
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"""Convert SI Volts to packed DAC channel group machine units.
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:param voltage: List of SI Volt voltages.
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@ -153,12 +167,12 @@ class Fastino:
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"""
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for i in range(len(voltage)):
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v = self.voltage_to_mu(voltage[i])
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if i & 1:
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if i & 1 != 0:
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v = data[i // 2] | (v << 16)
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data[i // 2] = int32(v)
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@kernel
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def set_dac(self, dac, voltage):
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def set_dac(self, dac: int32, voltage: float):
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"""Set DAC data to given voltage.
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:param dac: DAC channel (0-31).
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@ -167,18 +181,18 @@ class Fastino:
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self.write(dac, self.voltage_to_mu(voltage))
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@kernel
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def set_group(self, dac, voltage):
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def set_group(self, dac: int32, voltage: list[float]):
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"""Set DAC group data to given voltage.
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:param dac: DAC channel (0-31).
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:param voltage: Desired output voltage.
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"""
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data = [int32(0)] * (len(voltage) // 2)
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data = [int32(0) for _ in range(len(voltage) // 2)]
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self.voltage_group_to_mu(voltage, data)
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self.set_group_mu(dac, data)
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@kernel
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def update(self, update):
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def update(self, update: int32):
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"""Schedule channels for update.
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:param update: Bit mask of channels to update (32 bit).
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@ -186,7 +200,7 @@ class Fastino:
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self.write(0x20, update)
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@kernel
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def set_hold(self, hold):
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def set_hold(self, hold: int32):
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"""Set channels to manual update.
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:param hold: Bit mask of channels to hold (32 bit).
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@ -194,7 +208,7 @@ class Fastino:
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self.write(0x21, hold)
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@kernel
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def set_cfg(self, reset=0, afe_power_down=0, dac_clr=0, clr_err=0):
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def set_cfg(self, reset: bool = False, afe_power_down: bool = False, dac_clr: bool = False, clr_err: bool = False):
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"""Set configuration bits.
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:param reset: Reset SPI PLL and SPI clock domain.
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@ -205,11 +219,11 @@ class Fastino:
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This clears the sticky red error LED. Must be cleared to enable
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error counting.
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"""
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self.write(0x22, (reset << 0) | (afe_power_down << 1) |
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(dac_clr << 2) | (clr_err << 3))
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self.write(0x22, (int32(reset) << 0) | (int32(afe_power_down) << 1) |
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(int32(dac_clr) << 2) | (int32(clr_err) << 3))
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@kernel
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def set_leds(self, leds):
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def set_leds(self, leds: int32):
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"""Set the green user-defined LEDs
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:param leds: LED status, 8 bit integer each bit corresponding to one
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@ -218,14 +232,14 @@ class Fastino:
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self.write(0x23, leds)
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@kernel
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def set_continuous(self, channel_mask):
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def set_continuous(self, channel_mask: int32):
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"""Enable continuous DAC updates on channels regardless of new data
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being submitted.
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"""
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self.write(0x25, channel_mask)
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@kernel
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def stage_cic_mu(self, rate_mantissa, rate_exponent, gain_exponent):
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def stage_cic_mu(self, rate_mantissa: int32, rate_exponent: int32, gain_exponent: int32):
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"""Stage machine unit CIC interpolator configuration.
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"""
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if rate_mantissa < 0 or rate_mantissa >= 1 << 6:
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@ -238,7 +252,7 @@ class Fastino:
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self.write(0x26, config)
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@kernel
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def stage_cic(self, rate) -> TInt32:
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def stage_cic(self, rate: int32) -> int32:
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"""Compute and stage interpolator configuration.
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This method approximates the desired interpolation rate using a 10 bit
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@ -269,12 +283,12 @@ class Fastino:
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while gain > 1 << gain_exponent:
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gain_exponent += 1
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gain_exponent += order*rate_exponent
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assert gain_exponent <= order*16
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# NAC3TODO assert gain_exponent <= order*16
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self.stage_cic_mu(rate_mantissa - 1, rate_exponent, gain_exponent)
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return rate_mantissa << rate_exponent
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@kernel
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def apply_cic(self, channel_mask):
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def apply_cic(self, channel_mask: int32):
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"""Apply the staged interpolator configuration on the specified channels.
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Each Fastino channel starting with gateware v0.2 includes a fourth order
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@ -36,6 +36,10 @@
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{
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"type": "grabber",
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"ports": [6]
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},
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{
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"type": "fastino",
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"ports": [7]
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}
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]
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}
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@ -9,6 +9,7 @@ from artiq.coredevice.ad9912 import AD9912
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from artiq.coredevice.sampler import Sampler
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from artiq.coredevice.edge_counter import EdgeCounter
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from artiq.coredevice.grabber import Grabber
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from artiq.coredevice.fastino import Fastino
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@nac3
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@ -23,6 +24,7 @@ class NAC3Devices(EnvExperiment):
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sampler0: KernelInvariant[Sampler]
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ttl0_counter: KernelInvariant[EdgeCounter]
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grabber0: KernelInvariant[Grabber]
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fastino0: KernelInvariant[Fastino]
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def build(self):
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self.setattr_device("core")
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@ -35,6 +37,7 @@ class NAC3Devices(EnvExperiment):
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self.setattr_device("sampler0")
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self.setattr_device("ttl0_counter")
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self.setattr_device("grabber0")
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self.setattr_device("fastino0")
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@kernel
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def run(self):
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