diff --git a/artiq/coredevice/ad9914.py b/artiq/coredevice/ad9914.py
index bd2ec4db0..d37efec8b 100644
--- a/artiq/coredevice/ad9914.py
+++ b/artiq/coredevice/ad9914.py
@@ -175,6 +175,10 @@ class AD9914:
           accumulator is set to the value it would have if the DDS had been
           running at the specified frequency since the start of the
           experiment.
+
+        .. warning:: This setting may become inconsistent when used as part of
+            a DMA recording. When using DMA, it is recommended to specify the
+            phase mode explicitly when calling :meth:`set` or :meth:`set_mu`.
         """
         self.phase_mode = phase_mode
 
@@ -190,6 +194,11 @@ class AD9914:
         The "frequency update" pulse is sent to the DDS with a fixed latency
         with respect to the current position of the time cursor.
 
+        When switching from other phase modes to the continuous phase mode,
+        there is no jump in the DDS phase. This is however not true when
+        using the continuous phase mode after playing back a DMA sequence
+        that contained the other phase modes.
+
         :param ftw: frequency to generate.
         :param pow: adds an offset to the phase.
         :param phase_mode: if specified, overrides the default phase mode set
diff --git a/artiq/coredevice/spi2.py b/artiq/coredevice/spi2.py
index 205251084..70210841e 100644
--- a/artiq/coredevice/spi2.py
+++ b/artiq/coredevice/spi2.py
@@ -186,6 +186,12 @@ class SPIMaster:
         This method is portable and can also be called from e.g.
         :meth:`__init__`.
 
+        .. warning:: If this method is called while recording a DMA
+        sequence, the playback of the sequence will not update the
+        driver state.
+        When required, update the driver state manually (by calling
+        this method) after playing back a DMA sequence.
+
         :param div: SPI clock divider (see: :meth:`set_config_mu`)
         :param length: SPI transfer length (see: :meth:`set_config_mu`)
         """