M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

Revert "artiq_flash: ignore RTM FPGA" 

Naive optimism.

This reverts commit 100bda2582.
This commit is contained in:
Sebastien Bourdeauducq 2017-12-31 13:23:26 +08:00
parent 100bda2582
commit a1b8bca1e6
1 changed files with 6 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
artiq/frontend/artiq_flash.py
View File

@ -147,8 +147,9 @@ class ProgrammerSayma(Programmer):
"adapter_khz 5000", "adapter_khz 5000",
"transport select jtag", "transport select jtag",
"source [find cpld/xilinx-xc7.cfg]", # tap 0, pld 0
"set CHIP XCKU040", "set CHIP XCKU040",
"source [find cpld/xilinx-xcu.cfg]", "source [find cpld/xilinx-xcu.cfg]", # tap 1, pld 1
"target create xcu.proxy testee -chain-position xcu.tap", "target create xcu.proxy testee -chain-position xcu.tap",
"set XILINX_USER1 0x02", "set XILINX_USER1 0x02",
@ -158,11 +159,11 @@ class ProgrammerSayma(Programmer):
] ]
self.init() self.init()
def load(self, bitfile): def load(self, bitfile, pld=1):
self.prog.append("pld load 0 {{{}}}".format(bitfile)) self.prog.append("pld load {} {{{}}}".format(pld, bitfile))
def proxy(self, proxy_bitfile): def proxy(self, proxy_bitfile, pld=1):
self.load(proxy_bitfile) self.load(proxy_bitfile, pld)
self.prog.append("reset halt") self.prog.append("reset halt")
def flash_binary(self, flashno, address, filename): def flash_binary(self, flashno, address, filename):