From a1b8bca1e691425b64cfec3c5973e14123ca4cef Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 31 Dec 2017 13:23:26 +0800 Subject: [PATCH] Revert "artiq_flash: ignore RTM FPGA" Naive optimism. This reverts commit 100bda2582eb939ae08bb395144e1e2f655016ce. --- artiq/frontend/artiq_flash.py | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/artiq/frontend/artiq_flash.py b/artiq/frontend/artiq_flash.py index 5f9f2f0db..eebbd9b8d 100755 --- a/artiq/frontend/artiq_flash.py +++ b/artiq/frontend/artiq_flash.py @@ -147,8 +147,9 @@ class ProgrammerSayma(Programmer): "adapter_khz 5000", "transport select jtag", + "source [find cpld/xilinx-xc7.cfg]", # tap 0, pld 0 "set CHIP XCKU040", - "source [find cpld/xilinx-xcu.cfg]", + "source [find cpld/xilinx-xcu.cfg]", # tap 1, pld 1 "target create xcu.proxy testee -chain-position xcu.tap", "set XILINX_USER1 0x02", @@ -158,11 +159,11 @@ class ProgrammerSayma(Programmer): ] self.init() - def load(self, bitfile): - self.prog.append("pld load 0 {{{}}}".format(bitfile)) + def load(self, bitfile, pld=1): + self.prog.append("pld load {} {{{}}}".format(pld, bitfile)) - def proxy(self, proxy_bitfile): - self.load(proxy_bitfile) + def proxy(self, proxy_bitfile, pld=1): + self.load(proxy_bitfile, pld) self.prog.append("reset halt") def flash_binary(self, flashno, address, filename):