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docs: fix syntax

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Robert Jördens 2022-09-23 16:22:21 +02:00
parent a0053f7a2b
commit a1a4545ed4
1 changed files with 17 additions and 23 deletions
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artiq/coredevice/phaser.py
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@ -92,14 +92,15 @@ class Phaser:
that have different features. Phaser mode and coredevice PHY are both that have different features. Phaser mode and coredevice PHY are both
both selected at gateware compile-time and need to match. both selected at gateware compile-time and need to match.
Phaser gateware | Coredevice PHY | Features per :class:`PhaserChannel` =============== ============== ===================================
--------------- | -------------- | ----------------------------------- Phaser gateware Coredevice PHY Features per :class:`PhaserChannel`
Base <= v0.5 | Base | Base (5 :class:`PhaserOscillator`) =============== ============== ===================================
Base >= v0.6 | Base | Base + Servo Base <= v0.5 Base Base (5 :class:`PhaserOscillator`)
Miqro >= v0.6 | Miqro | :class:`Miqro` Base >= v0.6 Base Base + Servo
Miqro >= v0.6 Miqro :class:`Miqro`
=============== ============== ===================================
Base mode **Base mode**
---------
The coredevice produces 2 IQ (in-phase and quadrature) data streams with 25 The coredevice produces 2 IQ (in-phase and quadrature) data streams with 25
MS/s and 14 bit per quadrature. Each data stream supports 5 independent MS/s and 14 bit per quadrature. Each data stream supports 5 independent
@ -131,15 +132,13 @@ class Phaser:
absolute phase with respect to other RTIO input and output events absolute phase with respect to other RTIO input and output events
(see `get_next_frame_mu()`). (see `get_next_frame_mu()`).
Miqro mode **Miqro mode**
----------
See :class:`Miqro` See :class:`Miqro`
Here the DAC operates in 4x interpolation. Here the DAC operates in 4x interpolation.
Analog flow **Analog flow**
-----------
The four analog DAC outputs are passed through anti-aliasing filters. The four analog DAC outputs are passed through anti-aliasing filters.
@ -158,8 +157,7 @@ class Phaser:
configured through a shared SPI bus that is accessed and controlled via configured through a shared SPI bus that is accessed and controlled via
FPGA registers. FPGA registers.
Servo **Servo**
-----
Each phaser output channel features a servo to control the RF output amplitude Each phaser output channel features a servo to control the RF output amplitude
using feedback from an ADC. The servo consists of a first order IIR (infinite using feedback from an ADC. The servo consists of a first order IIR (infinite
@ -1193,8 +1191,8 @@ class PhaserChannel:
Gains are given in units of output full per scale per input full scale. Gains are given in units of output full per scale per input full scale.
.. note:: Due to inherent constraints of the fixed point datatypes and IIR .. note:: Due to inherent constraints of the fixed point datatypes and IIR
filters, the ``x_offset`` (setpoint) resolution depends on the selected gains. filters, the ``x_offset`` (setpoint) resolution depends on the selected
Low ``ki`` gains will lead to a low ``x_offset`` resolution. gains. Low ``ki`` gains will lead to a low ``x_offset`` resolution.
The transfer function is (up to time discretization and The transfer function is (up to time discretization and
coefficient quantization errors): coefficient quantization errors):
@ -1323,8 +1321,7 @@ class Miqro:
contained in the Phaser gateware. The output is generated by with contained in the Phaser gateware. The output is generated by with
the following data flow: the following data flow:
Oscillators **Oscillators**
...........
* There are n_osc = 16 oscillators with oscillator IDs 0..n_osc-1. * There are n_osc = 16 oscillators with oscillator IDs 0..n_osc-1.
* Each oscillator outputs one tone at any given time * Each oscillator outputs one tone at any given time
@ -1359,16 +1356,14 @@ class Miqro:
during fast pulse sequences. They are intended for use in calibration and during fast pulse sequences. They are intended for use in calibration and
initialization. initialization.
Summation **Summation**
.........
* The oscillator outputs are added together (wrapping addition). * The oscillator outputs are added together (wrapping addition).
* The user must ensure that the sum of oscillators outputs does not exceed the * The user must ensure that the sum of oscillators outputs does not exceed the
data range. In general that means that the sum of the amplitudes must not data range. In general that means that the sum of the amplitudes must not
exceed one. exceed one.
Shaper **Shaper**
......
* The summed complex output stream is then multiplied with a the complex-valued * The summed complex output stream is then multiplied with a the complex-valued
output of a triggerable shaper. output of a triggerable shaper.
@ -1393,8 +1388,7 @@ class Miqro:
each window respectively. This is used to implement pulses with arbitrary each window respectively. This is used to implement pulses with arbitrary
length or CW output. length or CW output.
Overall properties **Overall properties**
..................
* The DAC may upconvert the signal by applying a frequency offset f1 with * The DAC may upconvert the signal by applying a frequency offset f1 with
phase p1. phase p1.