mirror of https://github.com/m-labs/artiq.git
urukul: _RegIOUpdate fixes
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@ -1,3 +1,5 @@
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from __future__ import annotations
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from numpy import int32, int64
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from numpy import int32, int64
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from artiq.language.core import *
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from artiq.language.core import *
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@ -427,6 +429,8 @@ class CPLD:
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cfg |= (profile & 7) << CFG_PROFILE
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cfg |= (profile & 7) << CFG_PROFILE
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self.cfg_write(cfg)
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self.cfg_write(cfg)
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@nac3
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class _RegIOUpdate:
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class _RegIOUpdate:
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core: KernelInvariant[Core]
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core: KernelInvariant[Core]
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cpld: KernelInvariant[CPLD]
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cpld: KernelInvariant[CPLD]
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@ -436,8 +440,12 @@ class _RegIOUpdate:
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self.cpld = cpld
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self.cpld = cpld
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@kernel
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@kernel
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def pulse(self, t: float):
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def pulse_mu(self, t: int64):
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cfg = self.cpld.cfg_reg
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cfg = self.cpld.cfg_reg
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self.cpld.cfg_write(cfg | (1 << CFG_IO_UPDATE))
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self.cpld.cfg_write(cfg | (1 << CFG_IO_UPDATE))
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delay(t)
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delay_mu(t)
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self.cpld.cfg_write(cfg)
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self.cpld.cfg_write(cfg)
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@kernel
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def pulse(self, t: float):
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self.pulse_mu(self.core.seconds_to_mu(t))
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