From a14666bc1559223ed00be6cd8af602e32c76dd4f Mon Sep 17 00:00:00 2001 From: Harry Ho Date: Mon, 6 Dec 2021 17:52:50 +0800 Subject: [PATCH] ad9154: re-adjust LMFCDel & LMFCVar for 1 GS/s (K=32) * @HarryMakes performed 25 consecutive power-cycles of Sayma, in 2-min intervals: * Results: MinDelay = 8, FALL_COUNT_Delay = 10 --- artiq/firmware/libboard_artiq/ad9154.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/artiq/firmware/libboard_artiq/ad9154.rs b/artiq/firmware/libboard_artiq/ad9154.rs index 717a06eb5..d232dcafc 100644 --- a/artiq/firmware/libboard_artiq/ad9154.rs +++ b/artiq/firmware/libboard_artiq/ad9154.rs @@ -327,8 +327,8 @@ pub fn setup(dacno: u8, linerate: u64) -> Result<(), &'static str> { // LMFCDel & LMFCVar were deduced from values of DYN_LINK_LATENCY_0 // gathered from repeated power-cycles; see datasheet (Rev. C) p.44 // "Link Delay Setup Example, Without Known Delay" - write(ad9154_reg::LMFC_DELAY_0, 10); - write(ad9154_reg::LMFC_DELAY_1, 10); + write(ad9154_reg::LMFC_DELAY_0, 14); + write(ad9154_reg::LMFC_DELAY_1, 14); write(ad9154_reg::LMFC_VAR_0, 4); // receive buffer delay write(ad9154_reg::LMFC_VAR_1, 4); write(ad9154_reg::SYNC_ERRWINDOW, 0); // +- 1/2 DAC clock