diff --git a/artiq/firmware/libboard_artiq/lib.rs b/artiq/firmware/libboard_artiq/lib.rs
index 3402a1d2f..6c26e8d0a 100644
--- a/artiq/firmware/libboard_artiq/lib.rs
+++ b/artiq/firmware/libboard_artiq/lib.rs
@@ -28,7 +28,7 @@ pub mod rpc_queue;
 #[cfg(has_si5324)]
 pub mod si5324;
 
-#[cfg(has_slave_fpga)]
+#[cfg(has_slave_fpga_cfg)]
 pub mod slave_fpga;
 #[cfg(has_serwb_phy_amc)]
 pub mod serwb;
diff --git a/artiq/firmware/runtime/main.rs b/artiq/firmware/runtime/main.rs
index d222d7f2d..f5c0a0202 100644
--- a/artiq/firmware/runtime/main.rs
+++ b/artiq/firmware/runtime/main.rs
@@ -82,7 +82,7 @@ fn startup() {
         _ => info!("UART log level set to INFO by default")
     }
 
-    #[cfg(has_slave_fpga)]
+    #[cfg(has_slave_fpga_cfg)]
     board_artiq::slave_fpga::load().expect("cannot load RTM FPGA gateware");
     #[cfg(has_serwb_phy_amc)]
     board_artiq::serwb::wait_init();
diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py
index b7aebf62f..6f34e8663 100755
--- a/artiq/gateware/targets/sayma_amc.py
+++ b/artiq/gateware/targets/sayma_amc.py
@@ -194,8 +194,7 @@ class Standalone(MiniSoC, AMPSoC):
             slave_fpga_cfg.init_b,
             slave_fpga_cfg.program_b,
         ])
-        self.csr_devices.append("slave_fpga_cfg")
-        # self.config["HAS_SLAVE_FPGA"] = None
+        # self.csr_devices.append("slave_fpga_cfg")
         self.config["SLAVE_FPGA_GATEWARE"] = 0x200000
 
         # AMC/RTM serwb