From a050335ada407b1b574f84a49a17a5894d84f03e Mon Sep 17 00:00:00 2001 From: Peter Drmota Date: Sun, 17 Jan 2021 14:45:23 +0000 Subject: [PATCH] coredevice: Change Urukul default single-tone profile to 7 This allows using the internal profile control in RAM modulation mode (which always starts to play back at profile 0) without competing for the content of the profile 0 register used in single tone mode. Signed-off-by: Peter Drmota --- RELEASE_NOTES.rst | 7 +++++-- artiq/coredevice/ad9910.py | 24 +++++++++++++++--------- artiq/coredevice/urukul.py | 2 +- 3 files changed, 21 insertions(+), 12 deletions(-) diff --git a/RELEASE_NOTES.rst b/RELEASE_NOTES.rst index c743f2005..e239cab25 100644 --- a/RELEASE_NOTES.rst +++ b/RELEASE_NOTES.rst @@ -70,8 +70,11 @@ Highlights: - Improved performance for kernel RPC involving list and array. * Coredevice SI to mu conversions now always return valid codes, or raise a ``ValueError``. * Zotino now exposes ``voltage_to_mu()`` -* ``ad9910``: The maximum amplitude scale factor is now ``0x3fff`` (was ``0x3ffe`` - before). +* ``ad9910``: + - The maximum amplitude scale factor is now ``0x3fff`` (was ``0x3ffe`` before). + - The default single-tone profile is now 7 (was 0). + - Added option to ``set_mu()`` that affects the ASF, FTW and POW registers + instead of the single-tone profile register. * Mirny now supports HW revision independent, human readable ``clk_sel`` parameters: "XO", "SMA", and "MMCX". Passing an integer is backwards compatible. * Dashboard: diff --git a/artiq/coredevice/ad9910.py b/artiq/coredevice/ad9910.py index 95ad66896..e55ddce95 100644 --- a/artiq/coredevice/ad9910.py +++ b/artiq/coredevice/ad9910.py @@ -236,7 +236,7 @@ class AD9910: """ self.bus.set_config_mu(urukul.SPI_CONFIG | spi.SPI_END, 24, urukul.SPIT_DDS_WR, self.chip_select) - self.bus.write((addr << 24) | (data << 8)) + self.bus.write((addr << 24) | ((data & 0xffff) << 8)) @kernel def write32(self, addr: TInt32, data: TInt32): @@ -481,8 +481,8 @@ class AD9910: @kernel def set_mu(self, ftw: TInt32, pow_: TInt32 = 0, asf: TInt32 = 0x3fff, phase_mode: TInt32 = _PHASE_MODE_DEFAULT, - ref_time_mu: TInt64 = int64(-1), profile: TInt32 = 0): - """Set profile 0 data in machine units. + ref_time_mu: TInt64 = int64(-1), profile: TInt32 = 7): + """Set DDS data in machine units. This uses machine units (FTW, POW, ASF). The frequency tuning word width is 32, the phase offset word width is 16, and the amplitude @@ -501,7 +501,8 @@ class AD9910: by :meth:`set_phase_mode` for this call. :param ref_time_mu: Fiducial time used to compute absolute or tracking phase updates. In machine units as obtained by `now_mu()`. - :param profile: Profile number to set (0-7, default: 0). + :param profile: Profile number to set (0-7, default: 7), or -1 to write + parameters to the ASF, FTW and POW registers instead. :return: Resulting phase offset word after application of phase tracking offset. When using :const:`PHASE_MODE_CONTINUOUS` in subsequent calls, use this value as the "current" phase. @@ -524,8 +525,13 @@ class AD9910: # is equivalent to an output pipeline latency. dt = int32(now_mu()) - int32(ref_time_mu) pow_ += dt * ftw * self.sysclk_per_mu >> 16 - self.write64(_AD9910_REG_PROFILE0 + profile, - (asf << 16) | (pow_ & 0xffff), ftw) + if profile < 0: + self.set_asf(asf) + self.set_ftw(ftw) + self.set_pow(pow_) + else: + self.write64(_AD9910_REG_PROFILE0 + profile, + (asf << 16) | (pow_ & 0xffff), ftw) delay_mu(int64(self.sync_data.io_update_delay)) self.cpld.io_update.pulse_mu(8) # assumes 8 mu > t_SYN_CCLK at_mu(now_mu() & ~7) # clear fine TSC again @@ -786,8 +792,8 @@ class AD9910: @kernel def set(self, frequency: TFloat, phase: TFloat = 0.0, amplitude: TFloat = 1.0, phase_mode: TInt32 = _PHASE_MODE_DEFAULT, - ref_time_mu: TInt64 = int64(-1), profile: TInt32 = 0): - """Set profile 0 data in SI units. + ref_time_mu: TInt64 = int64(-1), profile: TInt32 = 7): + """Set DDS data in SI units. .. seealso:: :meth:`set_mu` @@ -796,7 +802,7 @@ class AD9910: :param amplitude: Amplitude in units of full scale :param phase_mode: Phase mode constant :param ref_time_mu: Fiducial time stamp in machine units - :param profile: Profile to affect + :param profile: Registers to affect :return: Resulting phase offset in turns """ return self.pow_to_turns(self.set_mu( diff --git a/artiq/coredevice/urukul.py b/artiq/coredevice/urukul.py index 7cda7a4ce..92b951036 100644 --- a/artiq/coredevice/urukul.py +++ b/artiq/coredevice/urukul.py @@ -188,7 +188,7 @@ class CPLD: assert sync_div is None sync_div = 0 - self.cfg_reg = urukul_cfg(rf_sw=rf_sw, led=0, profile=0, + self.cfg_reg = urukul_cfg(rf_sw=rf_sw, led=0, profile=7, io_update=0, mask_nu=0, clk_sel=clk_sel, sync_sel=sync_sel, rst=0, io_rst=0, clk_div=clk_div)