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spi2: xfers take one more cycle until ~busy

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Robert Jördens 2018-03-08 15:22:07 +00:00 committed by Robert Jordens
parent 5af4609053
commit a04bd5a4fd
1 changed files with 1 additions and 1 deletions
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artiq/coredevice/spi2.py
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@ -162,7 +162,7 @@ class SPIMaster:
raise ValueError("Invalid SPI transfer length") raise ValueError("Invalid SPI transfer length")
if div > 257 or div < 2: if div > 257 or div < 2:
raise ValueError("Invalid SPI clock divider") raise ValueError("Invalid SPI clock divider")
self.xfer_duration_mu = (length + 1)*div*self.ref_period_mu self.xfer_duration_mu = ((length + 1)*div + 1)*self.ref_period_mu
rtio_output(now_mu(), self.channel, SPI_CONFIG_ADDR, flags | rtio_output(now_mu(), self.channel, SPI_CONFIG_ADDR, flags |
((length - 1) << 8) | ((div - 2) << 16) | (cs << 24)) ((length - 1) << 8) | ((div - 2) << 16) | (cs << 24))
delay_mu(self.ref_period_mu) delay_mu(self.ref_period_mu)