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firmware: move wait for write completion to read()

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This commit is contained in:
Robert Jördens 2018-03-01 11:37:33 +01:00
parent a6ae08d8b8
commit a04a36ee36
3 changed files with 4 additions and 5 deletions
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2
artiq/firmware/libboard_artiq/ad9154.rs
View File

@ -22,13 +22,13 @@ fn write(addr: u16, data: u8) {
while csr::converter_spi::writable_read() == 0 {} while csr::converter_spi::writable_read() == 0 {}
csr::converter_spi::data_write( csr::converter_spi::data_write(
((addr as u32) << 16) | ((data as u32) << 8)); ((addr as u32) << 16) | ((data as u32) << 8));
while csr::converter_spi::writable_read() == 0 {}
} }
} }
fn read(addr: u16) -> u8 { fn read(addr: u16) -> u8 {
unsafe { unsafe {
write((1 << 15) | addr, 0); write((1 << 15) | addr, 0);
while csr::converter_spi::writable_read() == 0 {}
csr::converter_spi::data_read() as u8 csr::converter_spi::data_read() as u8
} }
} }

3
artiq/firmware/libboard_artiq/hmc830_7043.rs
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@ -78,7 +78,6 @@ mod hmc830 {
unsafe { unsafe {
while csr::converter_spi::writable_read() == 0 {} while csr::converter_spi::writable_read() == 0 {}
csr::converter_spi::data_write(val << 1); // last clk cycle loads data csr::converter_spi::data_write(val << 1); // last clk cycle loads data
while csr::converter_spi::writable_read() == 0 {}
} }
} }
@ -88,6 +87,7 @@ mod hmc830 {
// the SPI round trip delay and stick with CPHA=0 // the SPI round trip delay and stick with CPHA=0
write((1 << 6) | addr, 0); write((1 << 6) | addr, 0);
unsafe { unsafe {
while csr::converter_spi::writable_read() == 0 {}
csr::converter_spi::data_read() & 0xffffff csr::converter_spi::data_read() & 0xffffff
} }
} }
@ -173,7 +173,6 @@ mod hmc7043 {
unsafe { unsafe {
while csr::converter_spi::writable_read() == 0 {} while csr::converter_spi::writable_read() == 0 {}
csr::converter_spi::data_write(val << 8); csr::converter_spi::data_write(val << 8);
while csr::converter_spi::writable_read() == 0 {}
} }
} }

4
artiq/firmware/libboard_artiq/spi.rs
View File

@ -7,7 +7,7 @@ mod imp {
return Err(()) return Err(())
} }
unsafe { unsafe {
while csr::converter_spi::idle_read() == 0 {} while csr::converter_spi::writable_read() == 0 {}
csr::converter_spi::offline_write(flags >> 0 & 1); csr::converter_spi::offline_write(flags >> 0 & 1);
csr::converter_spi::end_write(flags >> 1 & 1); csr::converter_spi::end_write(flags >> 1 & 1);
// input (in RTIO): flags >> 2 & 1 // input (in RTIO): flags >> 2 & 1
@ -38,7 +38,6 @@ mod imp {
unsafe { unsafe {
while csr::converter_spi::writable_read() == 0 {} while csr::converter_spi::writable_read() == 0 {}
csr::converter_spi::data_write(data); csr::converter_spi::data_write(data);
while csr::converter_spi::writable_read() == 0 {}
} }
Ok(()) Ok(())
} }
@ -48,6 +47,7 @@ mod imp {
return Err(()) return Err(())
} }
Ok(unsafe { Ok(unsafe {
while csr::converter_spi::writable_read() == 0 {}
csr::converter_spi::data_read() csr::converter_spi::data_read()
}) })
} }