diff --git a/artiq/firmware/libboard_artiq/ad9154.rs b/artiq/firmware/libboard_artiq/ad9154.rs
index a50d55ab8..9cd40b169 100644
--- a/artiq/firmware/libboard_artiq/ad9154.rs
+++ b/artiq/firmware/libboard_artiq/ad9154.rs
@@ -22,13 +22,13 @@ fn write(addr: u16, data: u8) {
         while csr::converter_spi::writable_read() == 0 {}
         csr::converter_spi::data_write(
             ((addr as u32) << 16) | ((data as u32) << 8));
-        while csr::converter_spi::writable_read() == 0 {}
     }
 }
 
 fn read(addr: u16) -> u8 {
     unsafe {
         write((1 << 15) | addr, 0);
+        while csr::converter_spi::writable_read() == 0 {}
         csr::converter_spi::data_read() as u8
     }
 }
diff --git a/artiq/firmware/libboard_artiq/hmc830_7043.rs b/artiq/firmware/libboard_artiq/hmc830_7043.rs
index 16e9c3e7d..44bf0f967 100644
--- a/artiq/firmware/libboard_artiq/hmc830_7043.rs
+++ b/artiq/firmware/libboard_artiq/hmc830_7043.rs
@@ -78,7 +78,6 @@ mod hmc830 {
         unsafe {
             while csr::converter_spi::writable_read() == 0 {}
             csr::converter_spi::data_write(val << 1);  // last clk cycle loads data
-            while csr::converter_spi::writable_read() == 0 {}
         }
     }
 
@@ -88,6 +87,7 @@ mod hmc830 {
         // the SPI round trip delay and stick with CPHA=0
         write((1 << 6) | addr, 0);
         unsafe {
+            while csr::converter_spi::writable_read() == 0 {}
             csr::converter_spi::data_read() & 0xffffff
         }
     }
@@ -173,7 +173,6 @@ mod hmc7043 {
         unsafe {
             while csr::converter_spi::writable_read() == 0 {}
             csr::converter_spi::data_write(val << 8);
-            while csr::converter_spi::writable_read() == 0 {}
         }
     }
 
diff --git a/artiq/firmware/libboard_artiq/spi.rs b/artiq/firmware/libboard_artiq/spi.rs
index c18daffc7..a48f77239 100644
--- a/artiq/firmware/libboard_artiq/spi.rs
+++ b/artiq/firmware/libboard_artiq/spi.rs
@@ -7,7 +7,7 @@ mod imp {
             return Err(())
         }
         unsafe {
-            while csr::converter_spi::idle_read() == 0 {}
+            while csr::converter_spi::writable_read() == 0 {}
             csr::converter_spi::offline_write(flags >> 0 & 1);
             csr::converter_spi::end_write(flags >> 1 & 1);
             // input (in RTIO): flags >> 2 & 1
@@ -38,7 +38,6 @@ mod imp {
         unsafe {
             while csr::converter_spi::writable_read() == 0 {}
             csr::converter_spi::data_write(data);
-            while csr::converter_spi::writable_read() == 0 {}
         }
         Ok(())
     }
@@ -48,6 +47,7 @@ mod imp {
             return Err(())
         }
         Ok(unsafe {
+            while csr::converter_spi::writable_read() == 0 {}
             csr::converter_spi::data_read()
         })
     }