From 9f96b6bcda7d998ba9555d6cc912f55839d38bb9 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 4 Oct 2018 10:41:01 +0800 Subject: [PATCH] kasli: use 125MHz DRTIO freq for testing --- artiq/gateware/targets/kasli.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py index 8fbaa0ec1..904464cbf 100755 --- a/artiq/gateware/targets/kasli.py +++ b/artiq/gateware/targets/kasli.py @@ -685,7 +685,7 @@ class _MasterBase(MiniSoC, AMPSoC): } mem_map.update(MiniSoC.mem_map) - def __init__(self, rtio_clk_freq=150e6, **kwargs): + def __init__(self, rtio_clk_freq=125e6, **kwargs): MiniSoC.__init__(self, cpu_type="or1k", sdram_controller_type="minicon", @@ -834,7 +834,7 @@ class _SatelliteBase(BaseSoC): } mem_map.update(BaseSoC.mem_map) - def __init__(self, rtio_clk_freq=150e6, **kwargs): + def __init__(self, rtio_clk_freq=125e6, **kwargs): BaseSoC.__init__(self, cpu_type="or1k", sdram_controller_type="minicon",