kasli: add SED lanes count option to HW description JSON file (#1745)

Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
This commit is contained in:
Etienne Wodey 2021-12-03 10:05:35 +01:00 committed by GitHub
parent b8e7add785
commit 9f830b86c0
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 19 additions and 9 deletions

View File

@ -20,6 +20,8 @@ Highlights:
- Exposes upconverter calibration and enabling/disabling of upconverter LO & RF outputs. - Exposes upconverter calibration and enabling/disabling of upconverter LO & RF outputs.
- Add helpers to align Phaser updates to the RTIO timeline (``get_next_frame_mu()``) - Add helpers to align Phaser updates to the RTIO timeline (``get_next_frame_mu()``)
* ``get()``, ``get_mu()``, ``get_att()``, and ``get_att_mu()`` functions added for AD9910 and AD9912 * ``get()``, ``get_mu()``, ``get_att()``, and ``get_att_mu()`` functions added for AD9910 and AD9912
* On Kasli, the number of FIFO lanes in the scalable events dispatcher (SED) can now be configured in
the JSON hardware description file.
* New hardware support: * New hardware support:
- HVAMP_8CH 8 channel HV amplifier for Fastino / Zotino - HVAMP_8CH 8 channel HV amplifier for Fastino / Zotino
* ``artiq_ddb_template`` generates edge-counter keys that start with the key of the corresponding * ``artiq_ddb_template`` generates edge-counter keys that start with the key of the corresponding

View File

@ -64,6 +64,13 @@
"type": "boolean", "type": "boolean",
"default": false "default": false
}, },
"sed_lanes": {
"type": "number",
"minimum": 1,
"maximum": 32,
"default": 8,
"description": "Number of FIFOs in the SED, must be a power of 2"
},
"peripherals": { "peripherals": {
"type": "array", "type": "array",
"items": { "items": {

View File

@ -135,12 +135,12 @@ class StandaloneBase(MiniSoC, AMPSoC):
self.config["HAS_SI5324"] = None self.config["HAS_SI5324"] = None
self.config["SI5324_SOFT_RESET"] = None self.config["SI5324_SOFT_RESET"] = None
def add_rtio(self, rtio_channels): def add_rtio(self, rtio_channels, sed_lanes=8):
self.submodules.rtio_crg = _RTIOCRG(self.platform) self.submodules.rtio_crg = _RTIOCRG(self.platform)
self.csr_devices.append("rtio_crg") self.csr_devices.append("rtio_crg")
fix_serdes_timing_path(self.platform) fix_serdes_timing_path(self.platform)
self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3) self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels) self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels, lane_count=sed_lanes)
self.csr_devices.append("rtio_core") self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc) self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")( self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
@ -375,13 +375,13 @@ class MasterBase(MiniSoC, AMPSoC):
self.csr_devices.append("rtio_crg") self.csr_devices.append("rtio_crg")
fix_serdes_timing_path(platform) fix_serdes_timing_path(platform)
def add_rtio(self, rtio_channels): def add_rtio(self, rtio_channels, sed_lanes=8):
# Only add MonInj core if there is anything to monitor # Only add MonInj core if there is anything to monitor
if any([len(c.probes) for c in rtio_channels]): if any([len(c.probes) for c in rtio_channels]):
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj") self.csr_devices.append("rtio_moninj")
self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels) self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels, lane_count=sed_lanes)
self.csr_devices.append("rtio_core") self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc) self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
@ -608,13 +608,13 @@ class SatelliteBase(BaseSoC):
self.csr_devices.append("rtio_crg") self.csr_devices.append("rtio_crg")
fix_serdes_timing_path(platform) fix_serdes_timing_path(platform)
def add_rtio(self, rtio_channels): def add_rtio(self, rtio_channels, sed_lanes=8):
# Only add MonInj core if there is anything to monitor # Only add MonInj core if there is anything to monitor
if any([len(c.probes) for c in rtio_channels]): if any([len(c.probes) for c in rtio_channels]):
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj") self.csr_devices.append("rtio_moninj")
self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels) self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels, lane_count=sed_lanes)
self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors) self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
self.submodules.cri_con = rtio.CRIInterconnectShared( self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.drtiosat.cri], [self.drtiosat.cri],

View File

@ -57,7 +57,8 @@ class GenericStandalone(StandaloneBase):
self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels) self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
self.rtio_channels.append(rtio.LogChannel()) self.rtio_channels.append(rtio.LogChannel())
self.add_rtio(self.rtio_channels) self.add_rtio(self.rtio_channels, sed_lanes=description["sed_lanes"])
if has_grabber: if has_grabber:
self.config["HAS_GRABBER"] = None self.config["HAS_GRABBER"] = None
self.add_csr_group("grabber", self.grabber_csr_group) self.add_csr_group("grabber", self.grabber_csr_group)
@ -94,7 +95,7 @@ class GenericMaster(MasterBase):
self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels) self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
self.rtio_channels.append(rtio.LogChannel()) self.rtio_channels.append(rtio.LogChannel())
self.add_rtio(self.rtio_channels) self.add_rtio(self.rtio_channels, sed_lanes=description["sed_lanes"])
if has_grabber: if has_grabber:
self.config["HAS_GRABBER"] = None self.config["HAS_GRABBER"] = None
self.add_csr_group("grabber", self.grabber_csr_group) self.add_csr_group("grabber", self.grabber_csr_group)
@ -127,7 +128,7 @@ class GenericSatellite(SatelliteBase):
self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels) self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
self.rtio_channels.append(rtio.LogChannel()) self.rtio_channels.append(rtio.LogChannel())
self.add_rtio(self.rtio_channels) self.add_rtio(self.rtio_channels, sed_lanes=description["sed_lanes"])
if has_grabber: if has_grabber:
self.config["HAS_GRABBER"] = None self.config["HAS_GRABBER"] = None
self.add_csr_group("grabber", self.grabber_csr_group) self.add_csr_group("grabber", self.grabber_csr_group)