From 9dfb0bfe1b77dfd2706a40f48cf174cd97c07eb4 Mon Sep 17 00:00:00 2001
From: Harry Ho <hh@m-labs.hk>
Date: Thu, 16 Sep 2021 11:39:59 +0800
Subject: [PATCH] gth_ultrascale: fix missing T/RXPROGDIVRESET

---
 artiq/gateware/drtio/transceiver/gth_ultrascale.py      | 4 ++--
 artiq/gateware/drtio/transceiver/gth_ultrascale_init.py | 5 +++++
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/artiq/gateware/drtio/transceiver/gth_ultrascale.py b/artiq/gateware/drtio/transceiver/gth_ultrascale.py
index ddc88037a..0bf4e9e4c 100644
--- a/artiq/gateware/drtio/transceiver/gth_ultrascale.py
+++ b/artiq/gateware/drtio/transceiver/gth_ultrascale.py
@@ -77,8 +77,6 @@ class GTHSingle(Module):
             p_ALIGN_PCOMMA_DET               ="FALSE",
             p_ALIGN_PCOMMA_VALUE             =0b0101111100,
             p_A_RXOSCALRESET                 =0b0,
-            p_A_RXPROGDIVRESET               =0b0,
-            p_A_TXPROGDIVRESET               =0b0,
             p_CBCC_DATA_SOURCE_SEL           ="ENCODED",
             p_CDR_SWAP_MODE_EN               =0b0,
             p_CHAN_BOND_KEEP_ALIGN           ="FALSE",
@@ -475,6 +473,7 @@ class GTHSingle(Module):
 
             # TX Startup/Reset
             i_GTTXRESET=tx_init.gtXxreset,
+            i_TXPROGDIVRESET=tx_init.gtXxprogdivreset,
             o_TXRESETDONE=tx_init.Xxresetdone,
             i_TXDLYSRESET=tx_init.Xxdlysreset if mode != "slave" else self.txdlysreset,
             o_TXDLYSRESETDONE=tx_init.Xxdlysresetdone,
@@ -501,6 +500,7 @@ class GTHSingle(Module):
 
             # RX Startup/Reset
             i_GTRXRESET=rx_init.gtXxreset,
+            i_RXPROGDIVRESET=rx_init.gtXxprogdivreset,
             o_RXRESETDONE=rx_init.Xxresetdone,
             i_RXDLYSRESET=rx_init.Xxdlysreset,
             o_RXPHALIGNDONE=rxphaligndone,
diff --git a/artiq/gateware/drtio/transceiver/gth_ultrascale_init.py b/artiq/gateware/drtio/transceiver/gth_ultrascale_init.py
index 30645b876..6e4e80d59 100644
--- a/artiq/gateware/drtio/transceiver/gth_ultrascale_init.py
+++ b/artiq/gateware/drtio/transceiver/gth_ultrascale_init.py
@@ -18,6 +18,8 @@ class GTHInit(Module):
         self.plllock = Signal()
         self.pllreset = Signal()
         self.gtXxreset = Signal()
+        # Reset signal for programmable divider: https://www.xilinx.com/support/answers/64103.html
+        self.gtXxprogdivreset = Signal()
         self.Xxresetdone = Signal()
         self.Xxdlysreset = Signal()
         self.Xxdlysresetdone = Signal()
@@ -46,10 +48,12 @@ class GTHInit(Module):
 
         # Deglitch FSM outputs driving transceiver asynch inputs
         gtXxreset = Signal()
+        gtXxprogdivreset = Signal()
         Xxdlysreset = Signal()
         Xxuserrdy = Signal()
         self.sync += [
             self.gtXxreset.eq(gtXxreset),
+            self.gtXxprogdivreset.eq(gtXxprogdivreset),
             self.Xxdlysreset.eq(Xxdlysreset),
             self.Xxuserrdy.eq(Xxuserrdy)
         ]
@@ -80,6 +84,7 @@ class GTHInit(Module):
 
         startup_fsm.act("RESET_ALL",
             gtXxreset.eq(1),
+            gtXxprogdivreset.eq(1),
             self.pllreset.eq(1),
             pll_reset_timer.wait.eq(1),
             If(pll_reset_timer.done,