mirror of https://github.com/m-labs/artiq.git
drtio: remove spurious signals
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@ -29,8 +29,6 @@ class RTPacketSatellite(Module):
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self.write_channel = Signal(16)
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self.write_address = Signal(16)
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self.write_data = Signal(512)
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self.write_overflow = Signal()
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self.write_underflow = Signal()
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self.read_channel = Signal(16)
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self.read_readable = Signal()
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