From 9c96ebf7d4224f06554d8d343b10dda90a116eab Mon Sep 17 00:00:00 2001 From: Yann Sionneau Date: Thu, 25 Jun 2015 03:06:03 +0200 Subject: [PATCH] nist_qc2: add fmc adapter io file --- artiq/gateware/nist_qc2.py | 77 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 artiq/gateware/nist_qc2.py diff --git a/artiq/gateware/nist_qc2.py b/artiq/gateware/nist_qc2.py new file mode 100644 index 000000000..7f93e4e49 --- /dev/null +++ b/artiq/gateware/nist_qc2.py @@ -0,0 +1,77 @@ +from mibuild.generic_platform import * + +fmc_adapter_io = [ + ("ttl", 0, Pins("LPC:LA00_CC_P"), IOStandard("LVTTL")), + ("ttl", 1, Pins("LPC:LA02_P"), IOStandard("LVTTL")), + ("ttl", 2, Pins("LPC:LA00_CC_N"), IOStandard("LVTTL")), + ("ttl", 3, Pins("LPC:LA02_N"), IOStandard("LVTTL")), + ("ttl", 4, Pins("LPC:LA01_CC_P"), IOStandard("LVTTL")), + ("ttl", 5, Pins("LPC:LA01_CC_N"), IOStandard("LVTTL")), + ("ttl", 6, Pins("LPC:LA06_P"), IOStandard("LVTTL")), + ("ttl", 7, Pins("LPC:LA06_N"), IOStandard("LVTTL")), + ("ttl", 8, Pins("LPC:LA05_P"), IOStandard("LVTTL")), + ("ttl", 9, Pins("LPC:LA05_N"), IOStandard("LVTTL")), + ("ttl", 10, Pins("LPC:LA10_P"), IOStandard("LVTTL")), + ("ttl", 11, Pins("LPC:LA09_P"), IOStandard("LVTTL")), + ("ttl", 12, Pins("LPC:LA10_N"), IOStandard("LVTTL")), + ("ttl", 13, Pins("LPC:LA09_N"), IOStandard("LVTTL")), + ("ttl", 14, Pins("LPC:LA13_P"), IOStandard("LVTTL")), + ("ttl", 15, Pins("LPC:LA14_P"), IOStandard("LVTTL")), + + ("dds", 0, + Subsignal("a", Pins("LPC:LA22_N LPC:LA21_P LPC:LA22_P LPC:LA19_N " + "LPC:LA20_N LPC:LA19_P LPC:LA20_P")), + Subsignal("d", Pins("LPC:LA15_N LPC:LA16_N LPC:LA15_P LPC:LA16_P " + "LPC:LA11_N LPC:LA12_N LPC:LA11_P LPC:LA12_P " + "LPC:LA07_N LPC:LA08_N LPC:LA07_P LPC:LA08_P " + "LPC:LA04_N LPC:LA03_N LPC:LA04_P LPC:LA03_P")), + Subsignal("sel", Pins("LPC:LA24_N LPC:LA29_P LPC:LA28_P LPC:LA29_N " + "LPC:LA28_N LPC:LA31_P LPC:LA30_P LPC:LA31_N " + "LPC:LA30_N LPC:LA33_P LPC:LA33_N")), + Subsignal("fud_n", Pins("LPC:LA21_N")), + Subsignal("wr_n", Pins("LPC:LA24_P")), + Subsignal("rd_n", Pins("LPC:LA25_N")), + Subsignal("rst_in", Pins("LPC:LA25_P")), + IOStandard("LVTTL")), + + ("i2c", 0, + Subsignal("scl", Pins("LPC:IIC_SLC")), + Subsignal("sda", Pins("LPC:IIC_SDA")), + IOStandard("LVCMOS25")), + + ("clk_m2c", 0, + Subsignal("p", Pins("LPC:CLK0_M2C_P")), + Subsignal("n", Pins("LPC:CLK0_M2C_N")), + IOStandard("LVDS")), + + ("clk_m2c", 1, + Subsignal("p", Pins("LPC:CLK1_M2C_P")), + Subsignal("n", Pins("LPC:CLK1_M2C_N")), + IOStandard("LVDS")), + + ("la32", 0, + Subsignal("p", Pins("LPC:LA32_P")), + Subsignal("n", Pins("LPC:LA32_N")), + IOStandard("LVDS")), + + ("spi", 0, + Subsignal("clk", Pins("LPC:LA13_N")), + Subsignal("ce", Pins("LPC:LA14_N")), + Subsignal("mosi", Pins("LPC:LA17_CC_P")), + Subsignal("miso", Pins("LPC:LA17_CC_N")), + IOStandard("LVTTL")), + + ("spi", 1, + Subsignal("clk", Pins("LPC:LA18_CC_P")), + Subsignal("ce", Pins("LPC:LA18_CC_N")), + Subsignal("mosi", Pins("LPC:LA23_P")), + Subsignal("miso", Pins("LPC:LA23_N")), + IOStandard("LVTTL")), + + ("spi", 2, + Subsignal("clk", Pins("LPC:LA27_P")), + Subsignal("ce", Pins("LPC:LA26_P")), + Subsignal("mosi", Pins("LPC:LA27_N")), + Subsignal("miso", Pins("LPC:LA26_N")), + IOStandard("LVTTL")), +]