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phaser: doc tweaks
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@ -77,10 +77,10 @@ class Phaser:
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> 30 MHz.
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> 30 MHz.
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The four 16 bit 500 MS/s DAC data streams are sent via a 32 bit parallel
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The four 16 bit 500 MS/s DAC data streams are sent via a 32 bit parallel
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LVDS bus operating at 1 Gb/s per pin pair and processed in the DAC. On the
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LVDS bus operating at 1 Gb/s per pin pair and processed in the DAC (Texas
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DAC 2x interpolation, sinx/x compensation, quadrature modulator
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Instruments DAC34H84). On the DAC 2x interpolation, sinx/x compensation,
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compensation, fine and coarse mixing as well as group delay capabilities
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quadrature modulator compensation, fine and coarse mixing as well as group
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are available.
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delay capabilities are available.
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The latency/group delay from the RTIO events setting
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The latency/group delay from the RTIO events setting
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:class:`PhaserOscillator` or :class:`PhaserChannel` DUC parameters all they
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:class:`PhaserOscillator` or :class:`PhaserChannel` DUC parameters all they
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@ -93,11 +93,12 @@ class Phaser:
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attenuators and are available on the front panel. The odd outputs are
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attenuators and are available on the front panel. The odd outputs are
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available at MMCX connectors on board.
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available at MMCX connectors on board.
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In the upconverter variant, each IQ output pair feeds a one quadrature
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In the upconverter variant, each IQ output pair feeds one quadrature
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upconverter with integrated PLL/VCO. This analog quadrature upconverter
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upconverter (Texas Instruments TRF372017) with integrated PLL/VCO. This
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supports offset tuning for carrier and sideband suppression. The output
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digitally configured analog quadrature upconverter supports offset tuning
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from the upconverter passes through the 31.5 dB range step attenuator and
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for carrier and sideband suppression. The output from the upconverter
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is available at the front panel.
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passes through the 31.5 dB range step attenuator and is available at the
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front panel.
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The DAC, the analog quadrature upconverters and the attenuators are
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The DAC, the analog quadrature upconverters and the attenuators are
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configured through a shared SPI bus that is accessed and controlled via
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configured through a shared SPI bus that is accessed and controlled via
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@ -461,8 +462,11 @@ class Phaser:
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:param patterm: List of four int32 containing the pattern
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:param patterm: List of four int32 containing the pattern
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:return: Bit error mask (16 bits)
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:return: Bit error mask (16 bits)
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"""
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"""
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if len(pattern) != 4:
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raise ValueError("pattern length out of bounds")
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for addr in range(len(pattern)):
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for addr in range(len(pattern)):
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self.dac_write(0x25 + addr, pattern[addr])
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self.dac_write(0x25 + addr, pattern[addr])
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# repeat the pattern twice
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self.dac_write(0x29 + addr, pattern[addr])
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self.dac_write(0x29 + addr, pattern[addr])
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delay(.1*ms)
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delay(.1*ms)
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for ch in range(2):
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for ch in range(2):
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@ -534,7 +538,7 @@ class PhaserChannel:
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@kernel
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@kernel
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def set_duc_cfg(self, clr=0, clr_once=0, select=0):
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def set_duc_cfg(self, clr=0, clr_once=0, select=0):
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"""Set the digital upconverter and interpolator configuration.
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"""Set the digital upconverter (DUC) and interpolator configuration.
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:param clr: Keep the phase accumulator cleared (persistent)
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:param clr: Keep the phase accumulator cleared (persistent)
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:param clr_once: Clear the phase accumulator for one cycle
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:param clr_once: Clear the phase accumulator for one cycle
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@ -555,7 +559,7 @@ class PhaserChannel:
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@kernel
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@kernel
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def set_duc_frequency(self, frequency):
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def set_duc_frequency(self, frequency):
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"""Set the DUC frequency.
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"""Set the DUC frequency in SI units.
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:param frequency: DUC frequency in Hz (passband from -200 MHz to
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:param frequency: DUC frequency in Hz (passband from -200 MHz to
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200 MHz, wrapping around at +- 250 MHz)
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200 MHz, wrapping around at +- 250 MHz)
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@ -565,7 +569,7 @@ class PhaserChannel:
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@kernel
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@kernel
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def set_duc_phase_mu(self, pow):
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def set_duc_phase_mu(self, pow):
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"""Set the DUC phase offset
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"""Set the DUC phase offset.
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:param pow: DUC phase offset word (16 bit)
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:param pow: DUC phase offset word (16 bit)
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"""
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"""
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@ -575,7 +579,7 @@ class PhaserChannel:
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@kernel
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@kernel
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def set_duc_phase(self, phase):
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def set_duc_phase(self, phase):
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"""Set the DUC phase.
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"""Set the DUC phase in SI units.
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:param phase: DUC phase in turns
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:param phase: DUC phase in turns
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"""
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"""
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@ -631,7 +635,7 @@ class PhaserChannel:
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@kernel
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@kernel
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def trf_write(self, data, readback=False):
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def trf_write(self, data, readback=False):
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"""Write 32 bits to upconverter.
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"""Write 32 bits to quadrature upconverter register.
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:param data: Register data (32 bit) containing encoded address
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:param data: Register data (32 bit) containing encoded address
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:param readback: Whether to return the read back MISO data
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:param readback: Whether to return the read back MISO data
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