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soc: add timer to kernel CPU system

This commit is contained in:
Sebastien Bourdeauducq 2016-03-03 13:19:17 +08:00
parent b83b113f3c
commit 9af12230c8
3 changed files with 19 additions and 5 deletions
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11
artiq/gateware/soc.py
View File

@ -1,5 +1,6 @@
from misoc.integration.soc_core import mem_decoder from misoc.integration.soc_core import mem_decoder
from misoc.cores import timer from misoc.cores import timer
from misoc.interconnect import wishbone
from artiq.gateware import amp from artiq.gateware import amp
@ -29,3 +30,13 @@ class AMPSoC:
self.mailbox.i2) self.mailbox.i2)
self.add_memory_region("mailbox", self.add_memory_region("mailbox",
self.mem_map["mailbox"] | 0x80000000, 4) self.mem_map["mailbox"] | 0x80000000, 4)
self.submodules.timer_kernel = timer.Timer()
timer_csrs = self.timer_kernel.get_csrs()
timerwb = wishbone.CSRBank(timer_csrs)
self.submodules += timerwb
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["timer_kernel"]),
timerwb.bus)
self.add_csr_region("timer_kernel",
self.mem_map["timer_kernel"] | 0x80000000, 32,
timer_csrs)

7
artiq/gateware/targets/kc705.py
View File

@ -83,7 +83,6 @@ class _RTIOCRG(Module, AutoCSR):
_ams101_dac = [ _ams101_dac = [
("ams101_dac", 0, ("ams101_dac", 0,
Subsignal("ldac", Pins("XADC:GPIO0")), Subsignal("ldac", Pins("XADC:GPIO0")),
Subsignal("clk", Pins("XADC:GPIO1")), Subsignal("clk", Pins("XADC:GPIO1")),
Subsignal("mosi", Pins("XADC:GPIO2")), Subsignal("mosi", Pins("XADC:GPIO2")),
@ -95,6 +94,7 @@ _ams101_dac = [
class _NIST_Ions(MiniSoC, AMPSoC): class _NIST_Ions(MiniSoC, AMPSoC):
csr_map = { csr_map = {
"timer_kernel": None, # mapped on Wishbone instead
"rtio": None, # mapped on Wishbone instead "rtio": None, # mapped on Wishbone instead
"rtio_crg": 13, "rtio_crg": 13,
"kernel_cpu": 14, "kernel_cpu": 14,
@ -103,8 +103,9 @@ class _NIST_Ions(MiniSoC, AMPSoC):
} }
csr_map.update(MiniSoC.csr_map) csr_map.update(MiniSoC.csr_map)
mem_map = { mem_map = {
"rtio": 0x20000000, # (shadow @0xa0000000) "timer_kernel": 0x10000000, # (shadow @0x90000000)
"mailbox": 0x70000000 # (shadow @0xf0000000) "rtio": 0x20000000, # (shadow @0xa0000000)
"mailbox": 0x70000000 # (shadow @0xf0000000)
} }
mem_map.update(MiniSoC.mem_map) mem_map.update(MiniSoC.mem_map)

6
artiq/gateware/targets/pipistrello.py
View File

@ -103,6 +103,7 @@ TIMESPEC "TSfix_ise4" = FROM "GRPsys_clk" TO "GRPrtio_clk" TIG;
class NIST_QC1(BaseSoC, AMPSoC): class NIST_QC1(BaseSoC, AMPSoC):
csr_map = { csr_map = {
"timer_kernel": None, # mapped on Wishbone instead
"rtio": None, # mapped on Wishbone instead "rtio": None, # mapped on Wishbone instead
"rtio_crg": 10, "rtio_crg": 10,
"kernel_cpu": 11, "kernel_cpu": 11,
@ -111,8 +112,9 @@ class NIST_QC1(BaseSoC, AMPSoC):
} }
csr_map.update(BaseSoC.csr_map) csr_map.update(BaseSoC.csr_map)
mem_map = { mem_map = {
"rtio": 0x20000000, # (shadow @0xa0000000) "timer_kernel": 0x10000000, # (shadow @0x90000000)
"mailbox": 0x70000000 # (shadow @0xf0000000) "rtio": 0x20000000, # (shadow @0xa0000000)
"mailbox": 0x70000000 # (shadow @0xf0000000)
} }
mem_map.update(BaseSoC.mem_map) mem_map.update(BaseSoC.mem_map)