Remove Pipistrello support

Closes #658
Closes #381

README.rst

@@ -12,8 +12,7 @@ The system features a high-level programming language that helps describing comp
 
 ARTIQ uses FPGA hardware to perform its time-critical tasks.
 It is designed to be portable to hardware platforms from different vendors and FPGA manufacturers.
-Currently, one configuration of a `low-cost open hardware FPGA board <http://pipistrello.saanlima.com/>`_ and several different configurations of a `high-end FPGA evaluation kit <http://www.xilinx.com/products/boards-and-kits/ek-k7-kc705-g.html>`_ are used and supported.
+Currently, several different configurations of a `high-end FPGA evaluation kit <http://www.xilinx.com/products/boards-and-kits/ek-k7-kc705-g.html>`_ are used and supported. This FPGA platform can be combined with any number of additional peripherals, either already accessible from ARTIQ or made accessible with little effort.
-Any of these FPGA platforms can be combined with any number of additional peripherals, either already accessible from ARTIQ or made accessible with little effort.
 
 Custom hardware components with widely extended capabilities and advanced support for scalable and fully distributed real-time control of experiments `are being designed <https://github.com/m-labs/artiq-hardware>`_.
 

RELEASE_NOTES.rst

@@ -19,7 +19,6 @@ Release notes
 * ``seconds_to_mu`` and ``mu_to_seconds`` have become methods of the core
   device driver (use e.g. ``self.core.seconds_to_mu()``).
 * AD9858 DDSes and NIST QC1 hardware are no longer supported.
-* The Pipistrello port now has exclusively TTLs.
 * The DDS class names and setup options have changed, this requires an update of
   the device database.
 * ``int(a, width=b)`` has been removed. Use ``int32(a)`` and ``int64(a)``.
@@ -30,6 +29,8 @@ Release notes
   raising exceptions.
 * Results are still saved when ``analyze`` raises an exception.
 * LinearScan and RandomScan have been consolidated into RangeScan.
+* The Pipistrello is no longer supported. For a low-cost ARTIQ setup, use either
+  ARTIQ 2.x with Pipistrello, or the future ARTIQ 4.x with Kasli.
 
 
 2.3

artiq/frontend/artiq_flash.py

@@ -72,14 +72,6 @@ def main():
             "runtime": 0xb00000,
             "storage": 0xb80000,
         },
-        "pipistrello": {
-            "chip": "xc6slx45",
-            "start": "xc6s_program xc6s.tap",
-            "gateware": 0x000000,
-            "bios": 0x170000,
-            "runtime": 0x180000,
-            "storage": 0x200000,
-        },
     }[opts.target]
 
     if opts.dir is None:

artiq/gateware/rtio/phy/ttl_serdes_spartan6.py

@@ -1,156 +0,0 @@
-# Copyright (C) 2014, 2015 Robert Jordens <jordens@gmail.com>
-
-from migen import *
-
-from artiq.gateware.rtio.phy import ttl_serdes_generic
-
-
-class _OSERDES2_8X(Module):
-    def __init__(self, pad, stb):
-        self.o = Signal(8)
-        self.t_in = Signal()
-        self.t_out = Signal()
-
-        # # #
-
-        cascade = Signal(4)
-        o = self.o
-        common = dict(p_DATA_RATE_OQ="SDR", p_DATA_RATE_OT="SDR",
-                      p_DATA_WIDTH=8, p_OUTPUT_MODE="SINGLE_ENDED", i_TRAIN=0,
-                      i_CLK0=ClockSignal("rtiox8"), i_CLK1=0,
-                      i_CLKDIV=ClockSignal("rio_phy"),
-                      i_IOCE=stb, i_OCE=1, i_TCE=1, i_RST=0,
-                      i_T4=self.t_in, i_T3=self.t_in,
-                      i_T2=self.t_in, i_T1=self.t_in)
-
-        self.specials += [
-            Instance("OSERDES2", p_SERDES_MODE="MASTER",
-                     i_D4=o[7], i_D3=o[6], i_D2=o[5], i_D1=o[4],
-                     i_SHIFTIN1=1, i_SHIFTIN2=1,
-                     i_SHIFTIN3=cascade[2], i_SHIFTIN4=cascade[3],
-                     o_SHIFTOUT1=cascade[0], o_SHIFTOUT2=cascade[1],
-                     o_OQ=pad, o_TQ=self.t_out, **common),
-            Instance("OSERDES2", p_SERDES_MODE="SLAVE",
-                     i_D4=o[3], i_D3=o[2], i_D2=o[1], i_D1=o[0],
-                     i_SHIFTIN1=cascade[0], i_SHIFTIN2=cascade[1],
-                     i_SHIFTIN3=1, i_SHIFTIN4=1,
-                     o_SHIFTOUT3=cascade[2], o_SHIFTOUT4=cascade[3],
-                     **common),
-        ]
-
-
-class _IOSERDES2_8X(Module):
-    def __init__(self, pad, stb):
-        self.o = Signal(8)
-        self.i = Signal(8)
-        self.oe = Signal()
-
-        # # #
-
-        pad_i = Signal()
-        pad_o = Signal()
-        cascade = Signal()
-        i = self.i
-        common = dict(p_BITSLIP_ENABLE="FALSE", p_DATA_RATE="SDR",
-                      p_DATA_WIDTH=8, p_INTERFACE_TYPE="RETIMED",
-                      i_BITSLIP=0, i_CE0=1, i_IOCE=stb,
-                      i_RST=0, i_CLK0=ClockSignal("rtiox8"), i_CLK1=0,
-                      i_CLKDIV=ClockSignal("rio_phy"))
-        self.specials += [
-            Instance("ISERDES2", p_SERDES_MODE="MASTER",
-                     o_Q4=i[7], o_Q3=i[6], o_Q2=i[5], o_Q1=i[4],
-                     o_SHIFTOUT=cascade, i_D=pad_i, i_SHIFTIN=0,
-                     **common),
-            Instance("ISERDES2", p_SERDES_MODE="SLAVE",
-                     o_Q4=i[3], o_Q3=i[2], o_Q2=i[1], o_Q1=i[0],
-                     i_D=0, i_SHIFTIN=cascade, **common),
-        ]
-
-        oserdes = _OSERDES2_8X(pad_o, stb)
-        self.submodules += oserdes
-        self.specials += Instance("IOBUF",
-                                  i_I=pad_o, o_O=pad_i, i_T=oserdes.t_out,
-                                  io_IO=pad)
-        self.comb += [
-            oserdes.t_in.eq(~self.oe),
-            oserdes.o.eq(self.o),
-        ]
-
-
-class Output_8X(ttl_serdes_generic.Output):
-    def __init__(self, pad, stb):
-        serdes = _OSERDES2_8X(pad, stb)
-        self.submodules += serdes
-        ttl_serdes_generic.Output.__init__(self, serdes)
-
-
-class InOut_8X(ttl_serdes_generic.InOut):
-    def __init__(self, pad, stb):
-        serdes = _IOSERDES2_8X(pad, stb)
-        self.submodules += serdes
-        ttl_serdes_generic.InOut.__init__(self, serdes)
-
-
-class _OSERDES2_4X(Module):
-    def __init__(self, pad, stb):
-        self.o = Signal(4)
-        self.t_in = Signal()
-        self.t_out = Signal()
-
-        # # #
-
-        o = self.o
-        self.specials += Instance("OSERDES2", p_SERDES_MODE="NONE",
-                                  p_DATA_RATE_OQ="SDR", p_DATA_RATE_OT="SDR",
-                                  p_DATA_WIDTH=4, p_OUTPUT_MODE="SINGLE_ENDED",
-                                  i_TRAIN=0, i_CLK0=ClockSignal("rtiox4"),
-                                  i_CLK1=0, i_CLKDIV=ClockSignal("rio_phy"),
-                                  i_IOCE=stb, i_OCE=1, i_TCE=1, i_RST=0,
-                                  i_T4=self.t_in, i_T3=self.t_in,
-                                  i_T2=self.t_in, i_T1=self.t_in,
-                                  i_D4=o[3], i_D3=o[2], i_D2=o[1], i_D1=o[0],
-                                  o_OQ=pad, o_TQ=self.t_out)
-
-
-class _IOSERDES2_4X(Module):
-    def __init__(self, pad, stb):
-        self.o = Signal(4)
-        self.i = Signal(4)
-        self.oe = Signal()
-
-        # # #
-
-        pad_i = Signal()
-        pad_o = Signal()
-        i = self.i
-        self.specials += Instance("ISERDES2", p_SERDES_MODE="NONE",
-                                  p_BITSLIP_ENABLE="FALSE", p_DATA_RATE="SDR",
-                                  p_DATA_WIDTH=4, p_INTERFACE_TYPE="RETIMED",
-                                  i_BITSLIP=0, i_CE0=1, i_IOCE=stb,
-                                  i_RST=0, i_CLK0=ClockSignal("rtiox4"),
-                                  i_CLK1=0, i_CLKDIV=ClockSignal("rio_phy"),
-                                  o_Q4=i[3], o_Q3=i[2], o_Q2=i[1], o_Q1=i[0],
-                                  i_D=pad_i, i_SHIFTIN=0)
-        oserdes = _OSERDES2_4X(pad_o, stb)
-        self.submodules += oserdes
-        self.specials += Instance("IOBUF",
-                                  i_I=pad_o, o_O=pad_i, i_T=oserdes.t_out,
-                                  io_IO=pad)
-        self.comb += [
-            oserdes.t_in.eq(~self.oe),
-            oserdes.o.eq(self.o),
-        ]
-
-
-class Output_4X(ttl_serdes_generic.Output):
-    def __init__(self, pad, stb):
-        serdes = _OSERDES2_4X(pad, stb)
-        self.submodules += serdes
-        ttl_serdes_generic.Output.__init__(self, serdes)
-
-
-class InOut_4X(ttl_serdes_generic.InOut):
-    def __init__(self, pad, stb):
-        serdes = _IOSERDES2_4X(pad, stb)
-        self.submodules += serdes
-        ttl_serdes_generic.InOut.__init__(self, serdes)

artiq/gateware/targets/pipistrello.py

@@ -1,238 +0,0 @@
-#!/usr/bin/env python3
-
-# Copyright (C) 2014, 2015 Robert Jordens <jordens@gmail.com>
-# Copyright (C) 2014, 2015 M-Labs Limited
-
-import argparse
-from fractions import Fraction
-
-from migen import *
-from migen.genlib.resetsync import AsyncResetSynchronizer
-from migen.genlib.cdc import MultiReg
-from migen.build.generic_platform import *
-
-from misoc.interconnect.csr import *
-from misoc.cores import gpio
-from misoc.targets.pipistrello import (BaseSoC, soc_pipistrello_args,
-                                       soc_pipistrello_argdict)
-from misoc.integration.builder import builder_args, builder_argdict
-
-from artiq.gateware.amp import AMPSoC, build_artiq_soc
-from artiq.gateware import rtio
-from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_spartan6, dds, spi
-from artiq import __version__ as artiq_version
-
-
-_pmod_spi = [
-    ("pmod_spi", 0,
-     Subsignal("cs_n", Pins("PMOD:0")),
-     Subsignal("mosi", Pins("PMOD:1")),
-     Subsignal("miso", Pins("PMOD:2")),
-     Subsignal("clk", Pins("PMOD:3")),
-     IOStandard("LVTTL")
-     ),
-    ("pmod_extended_spi", 0,
-     Subsignal("cs_n", Pins("PMOD:0")),
-     Subsignal("mosi", Pins("PMOD:1")),
-     Subsignal("miso", Pins("PMOD:2")),
-     Subsignal("clk", Pins("PMOD:3")),
-     Subsignal("int", Pins("PMOD:4")),
-     Subsignal("rst", Pins("PMOD:5")),
-     Subsignal("d0", Pins("PMOD:6")),
-     Subsignal("d1", Pins("PMOD:7")),
-     IOStandard("LVTTL")
-     ),
-]
-
-
-class _RTIOCRG(Module, AutoCSR):
-    def __init__(self, platform, clk_freq):
-        self._clock_sel = CSRStorage()
-        self._pll_reset = CSRStorage(reset=1)
-        self._pll_locked = CSRStatus()
-
-        self.clock_domains.cd_rtio = ClockDomain()
-        self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
-        self.clock_domains.cd_rtiox8 = ClockDomain(reset_less=True)
-        self.rtiox4_stb = Signal()
-        self.rtiox8_stb = Signal()
-
-        rtio_f = 125*1000*1000
-        f = Fraction(rtio_f, clk_freq)
-        rtio_internal_clk = Signal()
-        rtio_external_clk = Signal()
-        ext_clk = platform.request("ext_clk")
-        dcm_locked = Signal()
-        rtio_clk = Signal()
-        pll_locked = Signal()
-        pll = Signal(3)
-        pll_fb = Signal()
-        self.specials += [
-            Instance("IBUFG", i_I=ext_clk, o_O=rtio_external_clk),
-            Instance("DCM_CLKGEN", p_CLKFXDV_DIVIDE=2,
-                     p_CLKFX_DIVIDE=f.denominator, p_CLKFX_MD_MAX=float(f),
-                     p_CLKFX_MULTIPLY=f.numerator, p_CLKIN_PERIOD=1e9/clk_freq,
-                     p_SPREAD_SPECTRUM="NONE", p_STARTUP_WAIT="FALSE",
-                     i_CLKIN=ClockSignal(), o_CLKFX=rtio_internal_clk,
-                     i_FREEZEDCM=0, i_RST=ResetSignal(), o_LOCKED=dcm_locked),
-            Instance("BUFGMUX",
-                     i_I0=rtio_internal_clk, i_I1=rtio_external_clk,
-                     i_S=self._clock_sel.storage, o_O=rtio_clk),
-            Instance("PLL_ADV", p_SIM_DEVICE="SPARTAN6",
-                     p_BANDWIDTH="OPTIMIZED", p_COMPENSATION="INTERNAL",
-                     p_REF_JITTER=.01, p_CLK_FEEDBACK="CLKFBOUT",
-                     i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0,
-                     i_RST=self._pll_reset.storage | ~dcm_locked, i_REL=0,
-                     p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=8,
-                     p_CLKFBOUT_PHASE=0., i_CLKINSEL=1,
-                     i_CLKIN1=rtio_clk, i_CLKIN2=0,
-                     p_CLKIN1_PERIOD=1e9/rtio_f, p_CLKIN2_PERIOD=0.,
-                     i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_locked,
-                     o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5,
-                     o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5,
-                     o_CLKOUT2=pll[2], p_CLKOUT2_DUTY_CYCLE=.5,
-                     p_CLKOUT0_PHASE=0., p_CLKOUT0_DIVIDE=1,
-                     p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=2,
-                     p_CLKOUT2_PHASE=0., p_CLKOUT2_DIVIDE=8),
-            Instance("BUFPLL", p_DIVIDE=8,
-                     i_PLLIN=pll[0], i_GCLK=self.cd_rtio.clk,
-                     i_LOCKED=pll_locked, o_IOCLK=self.cd_rtiox8.clk,
-                     o_SERDESSTROBE=self.rtiox8_stb),
-            Instance("BUFPLL", p_DIVIDE=4,
-                     i_PLLIN=pll[1], i_GCLK=self.cd_rtio.clk,
-                     i_LOCKED=pll_locked, o_IOCLK=self.cd_rtiox4.clk,
-                     o_SERDESSTROBE=self.rtiox4_stb),
-            Instance("BUFG", i_I=pll[2], o_O=self.cd_rtio.clk),
-            AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
-            MultiReg(pll_locked, self._pll_locked.status),
-        ]
-
-        # ISE infers correct period constraints for cd_rtio.clk from
-        # the internal clock. The first two TIGs target just the BUFGMUX.
-        platform.add_platform_command(
-            """
-NET "sys_clk" TNM_NET = "GRPsys_clk";
-NET "{ext_clk}" TNM_NET = "GRPext_clk";
-TIMESPEC "TSfix_ise1" = FROM "GRPsys_clk" TO "GRPext_clk" TIG;
-NET "{int_clk}" TNM_NET = "GRPint_clk";
-TIMESPEC "TSfix_ise2" = FROM "GRPsys_clk" TO "GRPint_clk" TIG;
-NET "{rtio_clk}" TNM_NET = "GRPrtio_clk";
-TIMESPEC "TSfix_ise3" = FROM "GRPrtio_clk" TO "GRPsys_clk" TIG;
-TIMESPEC "TSfix_ise4" = FROM "GRPsys_clk" TO "GRPrtio_clk" TIG;
-""",
-            ext_clk=rtio_external_clk, int_clk=rtio_internal_clk,
-            rtio_clk=self.cd_rtio.clk)
-
-
-_ttl_io = [
-    ("ext_clk", 0, Pins("C:15"), IOStandard("LVTTL")),
-
-    ("ttl", 0, Pins("B:0"), IOStandard("LVTTL")),
-    ("ttl", 1, Pins("B:1"), IOStandard("LVTTL")),
-    ("ttl", 2, Pins("B:2"), IOStandard("LVTTL")),
-    ("ttl", 3, Pins("B:3"), IOStandard("LVTTL")),
-    ("ttl", 4, Pins("B:4"), IOStandard("LVTTL")),
-    ("ttl", 5, Pins("B:5"), IOStandard("LVTTL")),
-    ("ttl", 6, Pins("B:6"), IOStandard("LVTTL")),
-    ("ttl", 7, Pins("B:7"), IOStandard("LVTTL")),
-
-    ("ttl", 8, Pins("B:8"), IOStandard("LVTTL")),
-    ("ttl", 9, Pins("B:9"), IOStandard("LVTTL")),
-    ("ttl", 10, Pins("B:10"), IOStandard("LVTTL")),
-    ("ttl", 11, Pins("B:11"), IOStandard("LVTTL")),
-    ("ttl", 12, Pins("B:12"), IOStandard("LVTTL")),
-    ("ttl", 13, Pins("B:13"), IOStandard("LVTTL")),
-    ("ttl", 14, Pins("B:14"), IOStandard("LVTTL")),
-    ("ttl", 15, Pins("B:15"), IOStandard("LVTTL")),
-]
-
-
-class Demo(BaseSoC, AMPSoC):
-    mem_map = {
-        "rtio":          0x20000000,  # (shadow @0xa0000000)
-        "mailbox":       0x70000000   # (shadow @0xf0000000)
-    }
-    mem_map.update(BaseSoC.mem_map)
-
-    def __init__(self, cpu_type="or1k", **kwargs):
-        BaseSoC.__init__(self,
-                         cpu_type=cpu_type,
-                         l2_size=64*1024,
-                         ident=artiq_version,
-                         clk_freq=75*1000*1000,
-                         **kwargs)
-        AMPSoC.__init__(self)
-
-        platform = self.platform
-
-        platform.toolchain.bitgen_opt += " -g compress"
-        platform.toolchain.ise_commands += """
-trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd {build_name}.pcf
-"""
-        platform.add_extension(_ttl_io)
-        platform.add_extension(_pmod_spi)
-
-        self.submodules.leds = gpio.GPIOOut(platform.request("user_led", 4))
-
-        self.submodules.rtio_crg = _RTIOCRG(platform, self.clk_freq)
-        self.csr_devices.append("rtio_crg")
-
-        # RTIO channels
-        rtio_channels = []
-        # the last TTL is used for ClockGen
-        for i in range(15):
-            if i in (0, 1):
-                phy = ttl_serdes_spartan6.InOut_4X(platform.request("ttl", i),
-                                                   self.rtio_crg.rtiox4_stb)
-            elif i in (2,):
-                phy = ttl_serdes_spartan6.Output_8X(platform.request("ttl", i),
-                                                    self.rtio_crg.rtiox8_stb)
-            else:
-                phy = ttl_simple.Output(platform.request("ttl", i))
-
-            self.submodules += phy
-            rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=128))
-
-        for led_number in range(4):
-            phy = ttl_simple.Output(platform.request("user_led", led_number))
-            self.submodules += phy
-            rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4))
-
-        phy = ttl_simple.ClockGen(platform.request("ttl", 15))
-        self.submodules += phy
-        rtio_channels.append(rtio.Channel.from_phy(phy))
-
-        phy = spi.SPIMaster(self.platform.request("pmod_extended_spi", 0))
-        self.submodules += phy
-        rtio_channels.append(rtio.Channel.from_phy(
-            phy, ofifo_depth=64, ififo_depth=64))
-
-        self.config["HAS_RTIO_LOG"] = None
-        self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
-        rtio_channels.append(rtio.LogChannel())
-
-        # RTIO logic
-        self.submodules.rtio_core = rtio.Core(rtio_channels)
-        self.csr_devices.append("rtio_core")
-        self.submodules.rtio = rtio.KernelInitiator(self.rtio_core.cri)
-        self.register_kernel_cpu_csrdevice("rtio")
-        self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
-        self.csr_devices.append("rtio_moninj")
-        self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_core.cri,
-                                                      self.get_native_sdram_if())
-        self.csr_devices.append("rtio_analyzer")
-
-
-def main():
-    parser = argparse.ArgumentParser(
-        description="ARTIQ device binary builder / Pipistrello demo")
-    builder_args(parser)
-    soc_pipistrello_args(parser)
-    args = parser.parse_args()
-
-    soc = Demo(**soc_pipistrello_argdict(args))
-    build_artiq_soc(soc, builder_argdict(args))
-
-
-if __name__ == "__main__":
-    main()

conda/artiq-pipistrello-demo/build.sh

@@ -1,14 +0,0 @@
-#!/bin/bash
-
-BUILD_SETTINGS_FILE=$HOME/.m-labs/build_settings.sh
-[ -f $BUILD_SETTINGS_FILE ] && . $BUILD_SETTINGS_FILE
-
-SOC_PREFIX=$PREFIX/lib/python3.5/site-packages/artiq/binaries/pipistrello-demo
-mkdir -p $SOC_PREFIX
-
-V=1 $PYTHON -m artiq.gateware.targets.pipistrello $MISOC_EXTRA_ISE_CMDLINE
-cp misoc_demo_pipistrello/gateware/top.bit $SOC_PREFIX
-cp misoc_demo_pipistrello/software/bios/bios.bin $SOC_PREFIX
-cp misoc_demo_pipistrello/software/runtime/runtime.fbi $SOC_PREFIX
-
-wget -P $SOC_PREFIX https://raw.githubusercontent.com/jordens/bscan_spi_bitstreams/master/bscan_spi_xc6slx45.bit

conda/artiq-pipistrello-demo/meta.yaml

@@ -1,22 +0,0 @@
-package:
-  name: artiq-pipistrello-demo
-  version: {{ environ.get("GIT_DESCRIBE_TAG", "") }}
-
-source:
-  git_url: ../..
-
-build:
-  noarch_python: true
-  number: {{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}
-  string: py_{{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}+git{{ environ.get("GIT_FULL_HASH", "")[:12] }}
-
-requirements:
-  build:
-    - artiq-dev {{ "{tag} py_{number}+git{hash}".format(tag=environ.get("GIT_DESCRIBE_TAG"), number=environ.get("GIT_DESCRIBE_NUMBER"), hash=environ.get("GIT_FULL_HASH", "")[:12]) if "GIT_DESCRIBE_TAG" in environ else "" }}
-  run:
-    - artiq {{ "{tag} py_{number}+git{hash}".format(tag=environ.get("GIT_DESCRIBE_TAG"), number=environ.get("GIT_DESCRIBE_NUMBER"), hash=environ.get("GIT_FULL_HASH", "")[:12]) if "GIT_DESCRIBE_TAG" in environ else "" }}
-
-about:
-  home: http://m-labs.hk/artiq
-  license: GPL
-  summary: 'Bitstream, BIOS and runtime for the Pipistrello board'

doc/manual/core_device.rst

@@ -152,46 +152,3 @@ The SAWG channels start with RTIO channel number 4, each occupying 3 channels.
 
 The board has one non-RTIO SPI bus that is accessible through
 :mod:`artiq.coredevice.ad9154`.
-
-
-Pipistrello
------------
-
-The low-cost Pipistrello FPGA board can be used as a lower-cost but slower alternative. Since the device does not have a native network interface, a PPP session is run over the serial port (which is then run over USB). To establish the PPP session with the core device, giving it the IP address 10.0.0.2, as root execute::
-
-    pppd /dev/ttyUSB1 115200 noauth nodetach local nocrtscts novj 10.0.0.1:10.0.0.2
-
-.. warning:: Windows is not supported.
-
-.. warning:: The Pipistrello draws a high current over USB, and that current increases when the FPGA design is active. If you experience problems such as intermittent board freezes or USB errors, try connecting it to a self-powered USB hub.
-
-The TTL lines are mapped to RTIO channels as follows:
-
-+--------------+------------+--------------+
-| RTIO channel | TTL line   | Capability   |
-+==============+============+==============+
-| 0-1          | B0-1       | Input+Output |
-+--------------+------------+--------------+
-| 2-14         | B2-14      | Output       |
-+--------------+------------+--------------+
-| 15           | USER_LED_1 | Output       |
-+--------------+------------+--------------+
-| 16           | USER_LED_2 | Output       |
-+--------------+------------+--------------+
-| 17           | USER_LED_3 | Output       |
-+--------------+------------+--------------+
-| 18           | USER_LED_4 | Output       |
-+--------------+------------+--------------+
-| 19           | B15        | Clock        |
-+--------------+------------+--------------+
-
-The board can accept an external RTIO clock connected to C15.
-
-The board has one RTIO SPI bus on the PMOD connector, compliant to PMOD
-Interface Type 2 (SPI) and 2A (expanded SPI):
-
-+--------------+--------+--------+--------+--------+
-| RTIO channel | CS_N   | MOSI   | MISO   | CLK    |
-+==============+========+========+========+========+
-| 16           | PMOD_0 | PMOD_1 | PMOD_2 | PMOD_3 |
-+--------------+--------+--------+--------+--------+

doc/manual/developing.rst

@@ -33,7 +33,7 @@ ARTIQ Anaconda development environment
     5. Add the ARTIQ source tree to the environment's search path::
 
            $ python setup.py develop
-    6. :ref:`Install Xilinx ISE or Vivado <install-xilinx>`
+    6. :ref:`Install Vivado <install-xilinx>`
     7. :ref:`Obtain and install the JTAG SPI flash proxy bitstream <install-bscan-spi>`
     8. :ref:`Configure OpenOCD <setup-openocd>`
     9. :ref:`Build target binaries <build-target-binaries>`
@@ -130,13 +130,11 @@ These steps are required to generate gateware bitstream (``.bit``) files, build
 
 .. _install-xilinx:
 
-* Install the FPGA vendor tools (i.e. Xilinx ISE and/or Vivado):
+* Install the FPGA vendor tools (i.e. Vivado):
 
-    * Get Xilinx tools from http://www.xilinx.com/support/download/index.htm. ISE can build gateware bitstreams both for boards using the Spartan-6 (Pipistrello) and 7-series devices (KC705), while Vivado supports only boards using 7-series devices.
+    * Get Vivado from http://www.xilinx.com/support/download/index.htm.
 
-    * The Pipistrello is supported by Webpack, the KC705 is not.
+    * During the Vivado installation, uncheck ``Install cable drivers`` (they are not required as we use better and open source alternatives).
-
-    * During the Xilinx toolchain installation, uncheck ``Install cable drivers`` (they are not required as we use better and open source alternatives).
 
 * Install Migen: ::
 
@@ -154,7 +152,7 @@ These steps are required to generate gateware bitstream (``.bit``) files, build
 
     The purpose of the flash proxy gateware bitstream is to give programming software fast JTAG access to the flash connected to the FPGA.
 
-    * Pipistrello and KC705:
+    * KC705:
 
         ::
 
@@ -210,15 +208,11 @@ These steps are required to generate gateware bitstream (``.bit``) files, build
 
 .. _build-target-binaries:
 
-    * For Pipistrello::
-
-        $ python3 -m artiq.gateware.targets.pipistrello
-
     * For KC705::
 
         $ python3 -m artiq.gateware.targets.kc705_dds -H nist_clock # or nist_qc2
 
-    .. note:: Add ``--toolchain ise`` if you wish to use ISE instead of Vivado.
+    .. note:: Add ``--toolchain ise`` if you wish to use ISE instead of Vivado. ISE needs a separate installation step.
 
 * Then, gather the binaries and flash them: ::
 
@@ -227,9 +221,7 @@ These steps are required to generate gateware bitstream (``.bit``) files, build
         $ cp misoc_nist_qcX_<board>/software/bios/bios.bin binaries
         $ cp misoc_nist_qcX_<board>/software/runtime/runtime.fbi binaries
         $ cd binaries
-        $ artiq_flash -d . -t <board>
+        $ artiq_flash -d .
-
-.. note:: The `-t` option specifies the board your are targeting. Available options are ``kc705`` and ``pipistrello``.
 
 * Check that the board boots by running a serial terminal program (you may need to press its FPGA reconfiguration button or power-cycle it to load the gateware bitstream that was newly written into the flash): ::
 

doc/manual/installing.rst

@@ -48,13 +48,12 @@ Then prepare to create a new conda environment with the ARTIQ package and the ma
 choose a suitable name for the environment, for example ``artiq-main`` if you intend to track the main label or ``artiq-2016-04-01`` if you consider the environment a snapshot of ARTIQ on 2016-04-01.
 Choose the package containing the binaries for your hardware:
 
-    * ``artiq-pipistrello-demo`` for the `Pipistrello <http://pipistrello.saanlima.com/>`_ board.
     * ``artiq-kc705-nist_clock`` for the KC705 board with the NIST "clock" FMC backplane and AD9914 DDS chips.
     * ``artiq-kc705-nist_qc2`` for the KC705 board with the NIST QC2 FMC backplane and AD9914 DDS chips.
 
 Conda will create the environment, automatically resolve, download, and install the necessary dependencies and install the packages you select::
 
-    $ conda create -n artiq-main artiq-pipistrello-demo
+    $ conda create -n artiq-main artiq-kc705-nist_clock
 
 After the installation, activate the newly created environment by name.
 On Unix::
@@ -78,7 +77,7 @@ When upgrading ARTIQ or when testing different versions it is recommended that n
 Keep previous environments around until you are certain that they are not needed anymore and a new environment is known to work correctly.
 You can create a new conda environment specifically to test a certain version of ARTIQ::
 
-    $ conda create -n artiq-test-1.0rc2 artiq-pipistrello-demo=1.0rc2
+    $ conda create -n artiq-test-1.0rc2 artiq-kc705-nist_clock=1.0rc2
 
 Switching between conda environments using ``$ source deactivate artiq-1.0rc2`` and ``$ source activate artiq-1.0rc1`` is the recommended way to roll back to previous versions of ARTIQ.
 You can list the environments you have created using::
@@ -123,7 +122,7 @@ On Windows, a third-party tool, `Zadig <http://zadig.akeo.ie/>`_, is necessary.
 
 1. Make sure the FPGA board's JTAG USB port is connected to your computer.
 2. Activate Options → List All Devices.
-3. Select the "Digilent Adept USB Device (Interface 0)" (for KC705) or "Pipistrello LX45" (for Pipistrello) device from the drop-down list.
+3. Select the "Digilent Adept USB Device (Interface 0)" device from the drop-down list.
 4. Select WinUSB from the spinner list.
 5. Click "Install Driver" or "Replace Driver".
 
@@ -136,17 +135,13 @@ Flashing the core device
 
 Then, you can flash the board:
 
-* For the Pipistrello board::
-
-    $ artiq_flash -t pipistrello -m demo
-
 * For the KC705 board (selecting the appropriate hardware peripheral)::
 
     $ artiq_flash -t kc705 -m [nist_clock/nist_qc2]
 
   The SW13 switches also need to be set to 00001.
 
-For the KC705, the next step is to flash the MAC and IP addresses to the board. See :ref:`those instructions <flash-mac-ip-addr>`.
+The next step is to flash the MAC and IP addresses to the board. See :ref:`those instructions <flash-mac-ip-addr>`.
 
 .. _configuring-core-device:
 

doc/manual/introduction.rst

@@ -13,8 +13,7 @@ The system features a high-level programming language that helps describing comp
 
 ARTIQ uses FPGA hardware to perform its time-critical tasks.
 It is designed to be portable to hardware platforms from different vendors and FPGA manufacturers.
-Currently, one configuration of a `low-cost open hardware FPGA board <http://pipistrello.saanlima.com/>`_ and several different configurations of a `high-end FPGA evaluation kit <http://www.xilinx.com/products/boards-and-kits/ek-k7-kc705-g.html>`_ are used and supported.
+Currently, several different configurations of a `high-end FPGA evaluation kit <http://www.xilinx.com/products/boards-and-kits/ek-k7-kc705-g.html>`_ are used and supported. This FPGA platform can be combined with any number of additional peripherals, either already accessible from ARTIQ or made accessible with little effort.
-Any of these FPGA platforms can be combined with any number of additional peripherals, either already accessible from ARTIQ or made accessible with little effort.
 
 Custom hardware components with widely extended capabilities and advanced support for scalable and fully distributed real-time control of experiments `are being designed <https://github.com/m-labs/artiq-hardware>`_.