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spi: fix xfers with full data_width (closes #615)

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misoc 15000af43611bbe8be13cb2b016e408f043202cd
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Robert Jördens 2017-01-03 19:50:15 +01:00
parent 6b7e6a53f7
commit 9a80b8d533
1 changed files with 8 additions and 3 deletions
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11
artiq/gateware/spi.py
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@ -138,7 +138,7 @@ class SPIMaster(Module):
assert len(xfer) <= len(bus.dat_w) assert len(xfer) <= len(bus.dat_w)
self.submodules.spi = spi = SPIMachine( self.submodules.spi = spi = SPIMachine(
data_width=len(bus.dat_w), data_width=len(bus.dat_w) + 1,
clock_width=len(config.div_read), clock_width=len(config.div_read),
bits_width=len(xfer.read_length)) bits_width=len(xfer.read_length))
@ -156,13 +156,18 @@ class SPIMaster(Module):
] ]
self.sync += [ self.sync += [
If(spi.done, If(spi.done,
data_read.eq(spi.reg.data), data_read.eq(
Mux(spi.reg.lsb, spi.reg.data[1:], spi.reg.data[:-1])),
), ),
If(spi.start, If(spi.start,
cs.eq(xfer.cs), cs.eq(xfer.cs),
spi.bits.n_write.eq(xfer.write_length), spi.bits.n_write.eq(xfer.write_length),
spi.bits.n_read.eq(xfer.read_length), spi.bits.n_read.eq(xfer.read_length),
spi.reg.data.eq(data_write), If(spi.reg.lsb,
spi.reg.data[:-1].eq(data_write),
).Else(
spi.reg.data[1:].eq(data_write),
),
pending.eq(0), pending.eq(0),
), ),
# wb.ack a transaction if any of the following: # wb.ack a transaction if any of the following: