drtio: order resets wrt writes

artiq/gateware/drtio/rt_controller.py

@@ -57,19 +57,6 @@ class RTController(Module):
             If(self.csrs.set_time.re, rt_packets.set_time_stb.eq(1))
         ]
 
-        # reset
-        self.sync += [
-            If(rt_packets.reset_ack, rt_packets.reset_stb.eq(0)),
-            If(self.csrs.reset.re,
-                rt_packets.reset_stb.eq(1),
-                rt_packets.reset_phy.eq(0)
-            ),
-            If(self.csrs.reset_phy.re,
-                rt_packets.reset_stb.eq(1),
-                rt_packets.reset_phy.eq(1)
-            ),
-        ]
-
         # remote channel status cache
         fifo_spaces_mem = Memory(16, channel_count)
         fifo_spaces = fifo_spaces_mem.get_port(write_capable=True)
@@ -80,6 +67,8 @@ class RTController(Module):
 
         # common packet fields
         rt_packets_fifo_request = Signal()
+        rt_packets_reset_request = Signal()
+        rt_packets_reset_phy_request = Signal()
         self.comb += [
             fifo_spaces.adr.eq(chan_sel),
             last_timestamps.adr.eq(chan_sel),
@@ -89,6 +78,10 @@ class RTController(Module):
             rt_packets.write_data.eq(self.cri.o_data),
             If(rt_packets_fifo_request,
                 rt_packets.write_timestamp.eq(0xffff000000000000)
+            ).Elif(rt_packets_reset_request,
+                rt_packets.write_timestamp.eq(0xffff000000000001)
+            ).Elif(rt_packets_reset_phy_request,
+                rt_packets.write_timestamp.eq(0xffff000000000003)
             ).Else(
                 rt_packets.write_timestamp.eq(self.cri.o_timestamp)
             )
@@ -141,6 +134,12 @@ class RTController(Module):
             ),
             If(self.csrs.o_get_fifo_space.re,
                 NextState("GET_FIFO_SPACE")
+            ),
+            If(self.csrs.reset.re,
+                NextState("RESET")
+            ),
+            If(self.csrs.reset_phy.re,
+                NextState("RESET_PHY")
             )
         )
         fsm.act("WRITE",
@@ -187,6 +186,22 @@ class RTController(Module):
                 NextState("IDLE")
             )
         )
+        fsm.act("RESET",
+            status_wait.eq(1),
+            rt_packets_reset_request.eq(1),
+            rt_packets.write_stb.eq(1),
+            If(rt_packets.write_ack,
+                NextState("IDLE")
+            )
+        )
+        fsm.act("RESET_PHY",
+            status_wait.eq(1),
+            rt_packets_reset_phy_request.eq(1),
+            rt_packets.write_stb.eq(1),
+            If(rt_packets.write_ack,
+                NextState("IDLE")
+            )
+        )
 
         # channel state access
         self.comb += [

artiq/gateware/drtio/rt_packets.py

@@ -430,6 +430,8 @@ class RTPacketMaster(Module):
         # all interface signals in sys domain unless otherwise specified
 
         # write interface, optimized for throughput
+        # writes, fifo space requests, and reset requests need to be ordered
+        # and all use the same FIFO.
         self.write_stb = Signal()
         self.write_ack = Signal()
         self.write_timestamp = Signal(64)
@@ -438,12 +440,16 @@ class RTPacketMaster(Module):
         self.write_data = Signal(512)
 
         # fifo space interface
-        # write with timestamp[48:] == 0xffff to make a fifo space request
+        # write with timestamp[48:] == 0xffff and timestamp[0] == 0
-        # (space requests have to be ordered wrt writes)
+        # to make a fifo space request
         self.fifo_space_not = Signal()
         self.fifo_space_not_ack = Signal()
         self.fifo_space = Signal(16)
 
+        # reset interface
+        # write with timestamp[48:] == 0xffff, timestamp[0] == 1,
+        # and timestamp[1] == phy to make a reset request
+
         # echo interface
         self.echo_stb = Signal()
         self.echo_ack = Signal()
@@ -457,11 +463,6 @@ class RTPacketMaster(Module):
         # a set_time request pending
         self.tsc_value = Signal(64)
 
-        # reset interface
-        self.reset_stb = Signal()
-        self.reset_ack = Signal()
-        self.reset_phy = Signal()
-
         # errors
         self.error_not = Signal()
         self.error_not_ack = Signal()
@@ -565,13 +566,6 @@ class RTPacketMaster(Module):
             self.set_time_stb, self.set_time_ack, None,
             set_time_stb, set_time_ack, None)
 
-        reset_stb = Signal()
-        reset_ack = Signal()
-        reset_phy = Signal()
-        self.submodules += _CrossDomainRequest("rtio",
-            self.reset_stb, self.reset_ack, self.reset_phy,
-            reset_stb, reset_ack, reset_phy)
-
         echo_stb = Signal()
         echo_ack = Signal()
         self.submodules += _CrossDomainRequest("rtio",
@@ -597,7 +591,11 @@ class RTPacketMaster(Module):
         tx_fsm.act("IDLE",
             If(wfb_readable,
                 If(write_timestamp[48:] == 0xffff,
-                    NextState("FIFO_SPACE")
+                    If(write_timestamp[0] == 0,
+                        NextState("FIFO_SPACE")
+                    ).Else(
+                        NextState("RESET")
+                    )
                 ).Else(
                     NextState("WRITE")
                 )
@@ -608,8 +606,6 @@ class RTPacketMaster(Module):
                 ).Elif(set_time_stb,
                     tsc_value_load.eq(1),
                     NextState("SET_TIME")
-                ).Elif(reset_stb,
-                    NextState("RESET")
                 )
             )
         )
@@ -659,9 +655,9 @@ class RTPacketMaster(Module):
             )
         )
         tx_fsm.act("RESET",
-            tx_dp.send("reset", phy=reset_phy),
+            tx_dp.send("reset", phy=write_timestamp[1]),
             If(tx_dp.packet_last,
-                reset_ack.eq(1),
+                wfb_re.eq(1),
                 NextState("IDLE")
             )
         )