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https://github.com/m-labs/artiq.git
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ad53xx: tweak spi readback
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a640041844
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@ -29,13 +29,13 @@ AD53XX_SPECIAL_OFS0 = 2 << 16
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AD53XX_SPECIAL_OFS1 = 3 << 16
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AD53XX_SPECIAL_READ = 5 << 16
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AD53XX_READ_X1A = 0X000 << 7
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AD53XX_READ_X1B = 0X040 << 7
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AD53XX_READ_OFFSET = 0X080 << 7
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AD53XX_READ_GAIN = 0X0C0 << 7
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AD53XX_READ_CONTROL = 0X101 << 7
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AD53XX_READ_OFS0 = 0X102 << 7
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AD53XX_READ_OFS1 = 0X103 << 7
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AD53XX_READ_X1A = 0x008 << 7
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AD53XX_READ_X1B = 0x048 << 7
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AD53XX_READ_OFFSET = 0x088 << 7
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AD53XX_READ_GAIN = 0x0C8 << 7
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AD53XX_READ_CONTROL = 0x101 << 7
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AD53XX_READ_OFS0 = 0x102 << 7
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AD53XX_READ_OFS1 = 0x103 << 7
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@portable
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@ -60,12 +60,11 @@ def ad53xx_cmd_read_ch(channel, op):
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:param channel: DAC channel to read (8 bits)
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:param op: The channel register to read, one of
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:const:`AD53XX_CMD_DATA`, :const:`AD53XX_CMD_OFFSET` or
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:const:`AD53XX_CMD_GAIN`
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:return: The 24-bit word to be written to the DAC
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:const:`AD53XX_READ_X1A`, :const:`AD53XX_READ_X1B`,
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:const:`AD53XX_READ_OFFSET`, :const:`AD53XX_CMD_GAIN` etc.
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:return: The 24-bit word to be written to the DAC to initiate read
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"""
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return (AD53XX_CMD_SPECIAL | AD53XX_SPECIAL_READ | op |
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((channel + 8) << 7))
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return (AD53XX_CMD_SPECIAL | AD53XX_SPECIAL_READ | (op + (channel << 7)))
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@portable
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@ -119,7 +118,7 @@ class AD53xx:
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"div_read", "vref", "core"}
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def __init__(self, dmgr, spi_device, ldac_device=None, clr_device=None,
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chip_select=1, div_write=4, div_read=8, vref=5.,
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chip_select=1, div_write=4, div_read=16, vref=5.,
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offset_dacs=8192, core="core"):
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self.bus = dmgr.get(spi_device)
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if ldac_device is None:
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@ -157,12 +156,12 @@ class AD53xx:
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"""Read a DAC register.
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This method advances the timeline by the duration of two SPI transfers
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plus two RTIO coarse cycles.
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plus two RTIO coarse cycles plus 270 ns and consumes all slack.
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:param channel: Channel number to read from (default :0)
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:param channel: Channel number to read from (default: 0)
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:param op: Operation to perform, one of :const:`AD53XX_READ_X1A`,
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:const:`AD53XX_READ_X1B`, :const:`AD53XX_READ_OFFSET`,
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:const:`AD53XX_READ_GAIN` (default: :const:`AD53XX_READ_X1A`).
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:const:`AD53XX_READ_GAIN` etc. (default: :const:`AD53XX_READ_X1A`).
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:return: The 16 bit register value
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"""
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self.bus.write(ad53xx_cmd_read_ch(channel, op) << 8)
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@ -170,10 +169,9 @@ class AD53xx:
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self.div_read, self.chip_select)
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delay(270*ns) # t_21 min sync high in readback
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self.bus.write((AD53XX_CMD_SPECIAL | AD53XX_SPECIAL_NOP) << 8)
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self.bus.set_config_mu(SPI_AD53XX_CONFIG, 24, self.div_write,
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self.chip_select)
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return self.bus.read()
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return self.bus.read() & 0xffff
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@kernel
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def write_offset_dacs_mu(self, value):
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