diff --git a/doc/manual/fpga_board_ports.rst b/doc/manual/fpga_board_ports.rst
index f66a3b339..eff4e3ac9 100644
--- a/doc/manual/fpga_board_ports.rst
+++ b/doc/manual/fpga_board_ports.rst
@@ -32,11 +32,7 @@ When plugged to a QC-DAQ LVDS adapter, the AD9858 DDS hardware can be used in ad
 +--------------+----------+-----------------+
 | 7            | TTL5     | Output only     |
 +--------------+----------+-----------------+
-| 8            | TTL6     | Output only     |
-+--------------+----------+-----------------+
-| 9            | TTL7     | Output only     |
-+--------------+----------+-----------------+
-| 10           | FUD      | DDS driver only |
+| 8            | FUD      | DDS driver only |
 +--------------+----------+-----------------+
 
 The input only limitation on channels 0 and 1 comes from the QC-DAQ adapter. When the adapter is not used (and physically unplugged from the Papilio Pro board), the corresponding pins on the Papilio Pro can be used as outputs. Do not configure these channels as outputs when the adapter is plugged, as this would cause electrical contention.
diff --git a/soc/runtime/rtio.c b/soc/runtime/rtio.c
index 1b6634fc7..f297196bf 100644
--- a/soc/runtime/rtio.c
+++ b/soc/runtime/rtio.c
@@ -95,7 +95,7 @@ int rtio_pileup_count(int channel)
     return r;
 }
 
-#define RTIO_FUD_CHANNEL 10
+#define RTIO_FUD_CHANNEL 8
 
 void rtio_fud_sync(void)
 {
diff --git a/soc/targets/artiq.py b/soc/targets/artiq.py
index 46ce96584..2e1676a4a 100644
--- a/soc/targets/artiq.py
+++ b/soc/targets/artiq.py
@@ -92,7 +92,7 @@ class ARTIQMiniSoC(BaseSoC):
             platform.request("ttl_h_tx_en").eq(1)
         ]
         rtio_ins = [platform.request("pmt") for i in range(2)]
-        rtio_outs = [platform.request("ttl", i) for i in range(8)] + [fud]
+        rtio_outs = [platform.request("ttl", i) for i in range(6)] + [fud]
 
         self.submodules.rtiocrg = _RTIOMiniCRG(platform)
         self.submodules.rtiophy = rtio.phy.SimplePHY(