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urukul: handle MSB in att_reg 

Signed-off-by: Robert Jördens <rj@quartiq.de>
This commit is contained in:
Robert Jördens 2018-11-09 13:19:44 +01:00
parent 9740032a94
commit 998be50f07
1 changed files with 1 additions and 1 deletions
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artiq/coredevice/urukul.py
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@ -174,7 +174,7 @@ class CPLD:
self.cfg_reg = urukul_cfg(rf_sw=rf_sw, led=0, profile=0, self.cfg_reg = urukul_cfg(rf_sw=rf_sw, led=0, profile=0,
io_update=0, mask_nu=0, clk_sel=clk_sel, io_update=0, mask_nu=0, clk_sel=clk_sel,
sync_sel=sync_sel, rst=0, io_rst=0) sync_sel=sync_sel, rst=0, io_rst=0)
self.att_reg = att self.att_reg = int32(att)
self.sync_div = sync_div self.sync_div = sync_div
@kernel @kernel