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gtp_7series: set clock muxes correctly for second QPLL channel

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This commit is contained in:
Sebastien Bourdeauducq 2018-01-23 10:39:20 +08:00
parent 25fee1a0bb
commit 98a5607634
1 changed files with 2 additions and 2 deletions
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4
artiq/gateware/drtio/transceiver/gtp_7series.py
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@ -86,7 +86,7 @@ class GTPSingle(Module):
p_TX_XCLK_SEL="TXUSR", p_TX_XCLK_SEL="TXUSR",
o_TXOUTCLK=self.txoutclk, o_TXOUTCLK=self.txoutclk,
p_TXOUT_DIV=2, p_TXOUT_DIV=2,
i_TXSYSCLKSEL=0b00, i_TXSYSCLKSEL=0b11,
i_TXOUTCLKSEL=0b11, i_TXOUTCLKSEL=0b11,
# TX Startup/Reset # TX Startup/Reset
@ -136,7 +136,7 @@ class GTPSingle(Module):
p_TX_CLK25_DIV=5, p_TX_CLK25_DIV=5,
p_RX_XCLK_SEL="RXUSR", p_RX_XCLK_SEL="RXUSR",
p_RXOUT_DIV=2, p_RXOUT_DIV=2,
i_RXSYSCLKSEL=0b00, i_RXSYSCLKSEL=0b11,
i_RXOUTCLKSEL=0b010, i_RXOUTCLKSEL=0b010,
o_RXOUTCLK=self.rxoutclk, o_RXOUTCLK=self.rxoutclk,
i_RXUSRCLK=ClockSignal("rtio_rx"), i_RXUSRCLK=ClockSignal("rtio_rx"),