mirror of https://github.com/m-labs/artiq.git
jesd204: remove ibuf_disable
We use the MOSFET to mute the HMC7043 noise on hardware v2 instead.
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1bc7743e03
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97a0dee3e8
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@ -20,7 +20,6 @@ class UltrascaleCRG(Module, AutoCSR):
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fabric_freq = int(125e6)
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fabric_freq = int(125e6)
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def __init__(self, platform, use_rtio_clock=False):
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def __init__(self, platform, use_rtio_clock=False):
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self.ibuf_disable = CSRStorage(reset=1)
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self.jreset = CSRStorage(reset=1)
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self.jreset = CSRStorage(reset=1)
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self.refclk = Signal()
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self.refclk = Signal()
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self.clock_domains.cd_jesd = ClockDomain()
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self.clock_domains.cd_jesd = ClockDomain()
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@ -29,7 +28,7 @@ class UltrascaleCRG(Module, AutoCSR):
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refclk_pads = platform.request("dac_refclk", 0)
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refclk_pads = platform.request("dac_refclk", 0)
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platform.add_period_constraint(refclk_pads.p, 1e9/self.refclk_freq)
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platform.add_period_constraint(refclk_pads.p, 1e9/self.refclk_freq)
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self.specials += [
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self.specials += [
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Instance("IBUFDS_GTE3", i_CEB=self.ibuf_disable.storage, p_REFCLK_HROW_CK_SEL=0b00,
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Instance("IBUFDS_GTE3", i_CEB=0, p_REFCLK_HROW_CK_SEL=0b00,
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i_I=refclk_pads.p, i_IB=refclk_pads.n,
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i_I=refclk_pads.p, i_IB=refclk_pads.n,
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o_O=self.refclk, o_ODIV2=refclk2),
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o_O=self.refclk, o_ODIV2=refclk2),
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AsyncResetSynchronizer(self.cd_jesd, self.jreset.storage),
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AsyncResetSynchronizer(self.cd_jesd, self.jreset.storage),
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