firmware: migrate analyzer_proto to new libio.

artiq/firmware/libproto/Cargo.toml

@@ -11,5 +11,6 @@ path = "lib.rs"
 byteorder = { version = "1.0", default-features = false }
 cslice = { version = "0.3" }
 log = { version = "0.4", default-features = false, optional = true }
+io = { path = "../libio", features = ["byteorder"] }
 std_artiq = { path = "../libstd_artiq", features = ["alloc"] }
 dyld = { path = "../libdyld" }

artiq/firmware/libproto/analyzer_proto.rs

@@ -1,5 +1,5 @@
-use std::io::{self, Write};
-use WriteExt;
+use io::{Write, Result};
+use io::proto::{ProtoWrite};
 
 #[derive(Debug)]
 pub struct Header {
@@ -11,7 +11,7 @@ pub struct Header {
 }
 
 impl Header {
-    pub fn write_to(&self, writer: &mut Write) -> io::Result<()> {
+    pub fn write_to<T: Write>(&self, writer: &mut T) -> Result<(), T::WriteError> {
         writer.write_u32(self.sent_bytes)?;
         writer.write_u64(self.total_byte_count)?;
         writer.write_u8(self.overflow_occurred as u8)?;

artiq/firmware/libproto/lib.rs

@@ -6,6 +6,7 @@ extern crate cslice;
 #[macro_use]
 extern crate log;
 
+extern crate io;
 extern crate dyld;
 extern crate std_artiq as std;
 

artiq/firmware/runtime/Cargo.toml

@@ -19,6 +19,7 @@ cslice = { version = "0.3" }
 log = { version = "0.4", default-features = false }
 managed = { version = "0.6", default-features = false, features = ["alloc", "map"] }
 unwind_backtrace = { path = "../libunwind_backtrace" }
+io = { path = "../libio", features = ["std_artiq"] }
 board = { path = "../libboard", features = ["uart_console", "smoltcp"] }
 alloc_list = { path = "../liballoc_list" }
 std_artiq = { path = "../libstd_artiq", features = ["alloc", "io_error_alloc"] }