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drtio: various fixes

This commit is contained in:
Sebastien Bourdeauducq 2016-10-17 19:23:08 +08:00
parent cce29e8b83
commit 9752ffe3d1
4 changed files with 29 additions and 16 deletions
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22
artiq/gateware/drtio/core.py
View File

@ -15,17 +15,17 @@ class DRTIOSatellite(Module):
] ]
link_layer_sync = SimpleNamespace( link_layer_sync = SimpleNamespace(
tx_aux_frame=self.link_layer.tx.aux_frame, tx_aux_frame=self.link_layer.tx_aux_frame,
tx_aux_data=self.link_layer.tx_aux_data, tx_aux_data=self.link_layer.tx_aux_data,
tx_aux_ack=self.link_layer.tx_aux_ack, tx_aux_ack=self.link_layer.tx_aux_ack,
tx_rt_frame=self.link_layer.tx_rt_frame, tx_rt_frame=self.link_layer.tx_rt_frame,
tx_rt_data=self.link_layer.tx_rt_data, tx_rt_data=self.link_layer.tx_rt_data,
rx_aux_stb=rx_synchronizer.sync(self.link_layer.rx_aux_stb), rx_aux_stb=rx_synchronizer.resync(self.link_layer.rx_aux_stb),
rx_aux_frame=rx_synchronizer.sync(self.link_layer.rx_aux_frame), rx_aux_frame=rx_synchronizer.resync(self.link_layer.rx_aux_frame),
rx_aux_data=rx_synchronizer.sync(self.link_layer.rx_aux_data), rx_aux_data=rx_synchronizer.resync(self.link_layer.rx_aux_data),
rx_rt_frame=rx_synchronizer.sync(self.link_layer.rx_rt_frame), rx_rt_frame=rx_synchronizer.resync(self.link_layer.rx_rt_frame),
rx_rt_data=rx_synchronizer.sync(self.link_layer.rx_rt_data) rx_rt_data=rx_synchronizer.resync(self.link_layer.rx_rt_data)
) )
self.submodules.rt_packets = ClockDomainsRenamer("rtio")( self.submodules.rt_packets = ClockDomainsRenamer("rtio")(
rt_packets.RTPacketSatellite(link_layer_sync)) rt_packets.RTPacketSatellite(link_layer_sync))
@ -33,6 +33,16 @@ class DRTIOSatellite(Module):
self.submodules.iot = ClockDomainsRenamer("rtio")( self.submodules.iot = ClockDomainsRenamer("rtio")(
iot.IOT(self.rt_packets, channels, fine_ts_width, full_ts_width)) iot.IOT(self.rt_packets, channels, fine_ts_width, full_ts_width))
# TODO: remote resets
self.clock_domains.cd_rio = ClockDomain()
self.clock_domains.cd_rio_phy = ClockDomain()
self.comb += [
self.cd_rio.clk.eq(ClockSignal("rtio")),
self.cd_rio.rst.eq(ResetSignal("rtio")),
self.cd_rio_phy.clk.eq(ClockSignal("rtio")),
self.cd_rio_phy.rst.eq(ResetSignal("rtio")),
]
class DRTIOMaster(Module): class DRTIOMaster(Module):
def __init__(self): def __init__(self):

11
artiq/gateware/drtio/iot.py
View File

@ -16,9 +16,10 @@ class IOT(Module):
) )
for n, channel in enumerate(channels): for n, channel in enumerate(channels):
data_width = rtlink.get_data_width(channel.interface) interface = channel.interface.o
address_width = rtlink.get_address_width(channel.interface) data_width = rtlink.get_data_width(interface)
fine_ts_width = rtlink.get_fine_ts_width(channel.interface) address_width = rtlink.get_address_width(interface)
fine_ts_width = rtlink.get_fine_ts_width(interface)
assert fine_ts_width <= max_fine_ts_width assert fine_ts_width <= max_fine_ts_width
# FIFO # FIFO
@ -47,7 +48,7 @@ class IOT(Module):
If(~fifo.writable, rt_packets.write_overflow.eq(1)), If(~fifo.writable, rt_packets.write_overflow.eq(1)),
If(rt_packets.write_underflow_ack, If(rt_packets.write_underflow_ack,
rt_packets.write_underflow.eq(0)), rt_packets.write_underflow.eq(0)),
If(rt_packets.timestamp[max_fine_ts_width:] < (tsc + 4), If(rt_packets.write_timestamp[max_fine_ts_width:] < (tsc + 4),
rt_packets.write_underflow.eq(1) rt_packets.write_underflow.eq(1)
) )
) )
@ -56,7 +57,7 @@ class IOT(Module):
if address_width: if address_width:
self.comb += fifo_in.address.eq(rt_packets.write_address) self.comb += fifo_in.address.eq(rt_packets.write_address)
self.comb += fifo_in.timestamp.eq( self.comb += fifo_in.timestamp.eq(
rt_packets.timestamp[max_fine_ts_width-fine_ts_width:]) rt_packets.write_timestamp[max_fine_ts_width-fine_ts_width:])
# FIFO read # FIFO read
self.sync += [ self.sync += [

10
artiq/gateware/drtio/transceiver/gtx_7series.py
View File

@ -8,6 +8,8 @@ from artiq.gateware.drtio.transceiver.gtx_7series_init import *
class GTX_1000BASE_BX10(Module): class GTX_1000BASE_BX10(Module):
rtio_clk_freq = 62.5e6
def __init__(self, clock_pads, tx_pads, rx_pads, sys_clk_freq): def __init__(self, clock_pads, tx_pads, rx_pads, sys_clk_freq):
self.submodules.encoder = ClockDomainsRenamer("rtio")( self.submodules.encoder = ClockDomainsRenamer("rtio")(
Encoder(2, True)) Encoder(2, True))
@ -33,7 +35,7 @@ class GTX_1000BASE_BX10(Module):
tx_init = GTXInit(sys_clk_freq, False) tx_init = GTXInit(sys_clk_freq, False)
# RX receives restart commands from RTIO domain # RX receives restart commands from RTIO domain
rx_init = ClockDomainsRenamer("rtio")( rx_init = ClockDomainsRenamer("rtio")(
GTXInit(62.5e6, True)) GTXInit(self.rtio_clk_freq, True))
self.submodules += tx_init, rx_init self.submodules += tx_init, rx_init
self.comb += tx_init.cplllock.eq(cplllock), \ self.comb += tx_init.cplllock.eq(cplllock), \
rx_init.cplllock.eq(cplllock), \ rx_init.cplllock.eq(cplllock), \
@ -166,7 +168,7 @@ class GTX_1000BASE_BX10(Module):
self.decoders[1].input.eq(rxdata[10:]) self.decoders[1].input.eq(rxdata[10:])
] ]
clock_aligner = BruteforceClockAligner(0b0011111000, 62.5e6) clock_aligner = BruteforceClockAligner(0b0011111000, self.rtio_clk_freq)
self.submodules += clock_aligner self.submodules += clock_aligner
self.comb += [ self.comb += [
clock_aligner.rxdata.eq(rxdata), clock_aligner.rxdata.eq(rxdata),
@ -193,7 +195,7 @@ class RXSynchronizer(Module, AutoCSR):
self.phase_shift = CSR() self.phase_shift = CSR()
self.phase_shift_done = CSRStatus() self.phase_shift_done = CSRStatus()
self.cd_rtio_delayed = ClockDomain(reset_less=True) self.clock_domains.cd_rtio_delayed = ClockDomain(reset_less=True)
mmcm_output = Signal() mmcm_output = Signal()
mmcm_fb = Signal() mmcm_fb = Signal()
@ -226,7 +228,7 @@ class RXSynchronizer(Module, AutoCSR):
Instance("BUFR", i_I=mmcm_output, o_O=self.cd_rtio_delayed.clk) Instance("BUFR", i_I=mmcm_output, o_O=self.cd_rtio_delayed.clk)
] ]
def sync(self, signal): def resync(self, signal):
delayed = Signal.like(signal, related=signal) delayed = Signal.like(signal, related=signal)
synchronized = Signal.like(signal, related=signal) synchronized = Signal.like(signal, related=signal)
self.sync.rtio_delayed += delayed.eq(signal) self.sync.rtio_delayed += delayed.eq(signal)

2
artiq/gateware/drtio/transceiver/gtx_7series_init.py
View File

@ -157,7 +157,7 @@ class BruteforceClockAligner(Module):
comma_seen_rxclk = Signal() comma_seen_rxclk = Signal()
comma_seen = Signal() comma_seen = Signal()
self.specials += MultiReg(comma_seen_rxclk, comma_seen) self.specials += MultiReg(comma_seen_rxclk, comma_seen)
comma_seen_reset = PulseSynchronizer("sys", "rx") comma_seen_reset = PulseSynchronizer("rtio", "rtio_rx")
self.submodules += comma_seen_reset self.submodules += comma_seen_reset
self.sync.rtio_rx += \ self.sync.rtio_rx += \
If(comma_seen_reset.o, If(comma_seen_reset.o,