mirror of https://github.com/m-labs/artiq.git
sayma_amc: remove dummy FPGA pin assignment testing code
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@ -444,17 +444,6 @@ class Satellite(BaseSoC, RTMCommon):
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self.crg.cd_sys.clk,
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gth.txoutclk, gth.rxoutclk)
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# placeholder code to test I/O routing and standards
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if self.hw_rev == "v2.0":
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self.clock_domains.cd_ddmtd_helper = ClockDomain(reset_less=True)
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helper_clk = platform.request("ddmtd_helper_clk")
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self.specials += Instance("IBUFGDS",
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i_I=helper_clk.p, i_IB=helper_clk.n,
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o_O=self.cd_ddmtd_helper.clk)
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ddmtd = platform.request("ddmtd_results")
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self.sync.ddmtd_helper += platform.request("tp16").eq(
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ddmtd.rec_clk ^ ddmtd.main_xo)
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def main():
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parser = argparse.ArgumentParser(
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