M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-19 00:16:29 +08:00
Code Issues Projects Releases Wiki Activity

kasli2: add false path constraint for wrpll helper clock

Browse Source
This commit is contained in:
Sebastien Bourdeauducq 2020-10-08 16:19:44 +08:00
parent 6248970ef8
commit 96a5df0dc6
1 changed files with 3 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
artiq/gateware/targets/kasli.py
View File

@ -614,6 +614,9 @@ class SatelliteBase(BaseSoC):
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
gtp.txoutclk, gtp.rxoutclk)
if with_wrpll:
platform.add_false_path_constraints(
self.wrpll.cd_helper.clk, gtp.rxoutclk)
for gtp in self.drtio_transceiver.gtps[1:]:
platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(