M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

rtio/sed: output network fixes

This commit is contained in:
Sebastien Bourdeauducq 2017-09-10 23:23:10 +08:00
parent 5646e19dc3
commit 96505a1cd9
1 changed files with 27 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

38
artiq/gateware/rtio/sed/output_network.py
View File

@ -15,8 +15,8 @@ def boms_get_partner(n, l, p):
return n + scale return n + scale
def boms_steps_pairs(node_count): def boms_steps_pairs(lane_count):
d = log2_int(node_count) d = log2_int(lane_count)
steps = [] steps = []
for l in range(1, d+1): for l in range(1, d+1):
for p in range(1, l+1): for p in range(1, l+1):
@ -34,20 +34,21 @@ def boms_steps_pairs(node_count):
return steps return steps
layout_rtio_payload = [ def layout_rtio_payload(fine_ts_width):
return [
("channel", 24), ("channel", 24),
("timestamp", 64), ("fine_ts", fine_ts_width),
("address", 16), ("address", 16),
("data", 512), ("data", 512),
] ]
def layout_node_data(seqn_size): def layout_node_data(seqn_width, fine_ts_width):
return [ return [
("valid", 1), ("valid", 1),
("seqn", seqn_size), ("seqn", seqn_width),
("replace_occured", 1), ("replace_occured", 1),
("payload", layout_rtio_payload) ("payload", layout_rtio_payload(fine_ts_width))
] ]
@ -56,25 +57,30 @@ def cmp_wrap(a, b):
class OutputNetwork(Module): class OutputNetwork(Module):
def __init__(self, node_count, seqn_size): def __init__(self, lane_count, seqn_width, fine_ts_width):
self.input = [Record(layout_node_data(seqn_size)) for _ in node_count] self.input = [Record(layout_node_data(seqn_width, fine_ts_width))
for _ in range(lane_count)]
self.output = None self.output = None
step_input = self.input step_input = self.input
for step in boms_steps_pairs(node_count): for step in boms_steps_pairs(lane_count):
step_output = [Record(layout_node_data(seqn_size)) for _ in node_count] step_output = [Record(layout_node_data(seqn_width, fine_ts_width))
for _ in range(lane_count)]
for node1, node2 in step: for node1, node2 in step:
self.sync += [ self.sync += [
If(step_input[node1].payload.channel == step_input[node2].payload.channel, If(step_input[node1].payload.channel == step_input[node2].payload.channel,
If(cmp_wrap(step_input[node1].seqn, step_input[node2].seqn), If(cmp_wrap(step_input[node1].seqn, step_input[node2].seqn),
step_output[node1].eq(step_output[node2]), step_output[node1].eq(step_input[node2]),
step_output[node2].eq(step_input[node1])
).Else( ).Else(
step_output[node1].eq(step_output[node1]), step_output[node1].eq(step_input[node1]),
step_output[node2].eq(step_input[node2])
), ),
If(step_input[node1].valid & step_input[node2].valid,
step_output[node1].replace_occured.eq(1), step_output[node1].replace_occured.eq(1),
step_output[node2].eq(step_input[node2]),
step_output[node2].valid.eq(0) step_output[node2].valid.eq(0)
)
).Elif(step_input[node1].payload.channel < step_input[node2].payload.channel, ).Elif(step_input[node1].payload.channel < step_input[node2].payload.channel,
step_output[node1].eq(step_input[node1]), step_output[node1].eq(step_input[node1]),
step_output[node2].eq(step_input[node2]) step_output[node2].eq(step_input[node2])
@ -84,7 +90,7 @@ class OutputNetwork(Module):
) )
] ]
unchanged = list(range(node_count)) unchanged = list(range(lane_count))
for node1, node2 in step: for node1, node2 in step:
unchanged.remove(node1) unchanged.remove(node1)
unchanged.remove(node2) unchanged.remove(node2)