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ad9154: mix mode addr, digital gain must be on

This commit is contained in:
Robert Jördens 2016-10-12 15:00:53 +02:00
parent 4376ef5615
commit 9644a3a362
2 changed files with 4 additions and 4 deletions
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2
artiq/coredevice/ad9154_reg.py
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@ -748,7 +748,7 @@ def AD9154_GROUPCOMP_BYPI_GET(x: TInt32) -> TInt32:
return (x >> 1) & 0x1
AD9154_MIX_MODE = 0x047
AD9154_MIX_MODE = 0x04a
AD9154_NCOALIGN_MODE = 0x050
# default: 0x00, access: R/W

6
artiq/examples/phaser/repository/dac_setup.py
View File

@ -106,7 +106,7 @@ class DACSetup(EnvExperiment):
self.ad9154.dac_write(AD9154_DATAPATH_CTRL,
AD9154_I_TO_Q_SET(0) | AD9154_SEL_SIDEBAND_SET(0) |
AD9154_MODULATION_TYPE_SET(0) | AD9154_PHASE_ADJ_ENABLE_SET(0) |
AD9154_DIG_GAIN_ENABLE_SET(0) | AD9154_INVSINC_ENABLE_SET(0))
AD9154_DIG_GAIN_ENABLE_SET(1) | AD9154_INVSINC_ENABLE_SET(0))
self.ad9154.dac_write(AD9154_IDAC_DIG_GAIN0, 0x00)
self.ad9154.dac_write(AD9154_IDAC_DIG_GAIN1, 0x8)
self.ad9154.dac_write(AD9154_QDAC_DIG_GAIN0, 0x00)
@ -181,8 +181,8 @@ class DACSetup(EnvExperiment):
self.ad9154.dac_write(AD9154_CTRLREG1, jesd_settings.transport.f)
self.ad9154.dac_write(AD9154_CTRLREG2, AD9154_ILAS_MODE_SET(0) |
AD9154_THRESHOLD_MASK_EN_SET(0))
self.ad9154.dac_write(AD9154_KVAL, 1) # *4*K multiframes during ILAS
self.ad9154.dac_write(AD9154_LANEENABLE, 0x0f)
self.ad9154.dac_write(AD9154_KVAL, 1) # *4*K multiframes during ILAS
self.ad9154.dac_write(AD9154_LANEENABLE, 0x0f) # CGS _after_ this
self.ad9154.dac_write(AD9154_TERM_BLK1_CTRLREG0, 1)
self.ad9154.dac_write(AD9154_TERM_BLK2_CTRLREG0, 1)