From 95d7cba34a0a2ff536f6bf339c786fe5cb76fd97 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 27 Sep 2016 12:46:01 +0800 Subject: [PATCH] drtio: fixes, add aux packet test --- artiq/gateware/drtio/link_layer.py | 11 ++- artiq/test/gateware/drtio/test_link_layer.py | 78 +++++++++++++++++--- 2 files changed, 75 insertions(+), 14 deletions(-) diff --git a/artiq/gateware/drtio/link_layer.py b/artiq/gateware/drtio/link_layer.py index aac149b4f..4f98a0a4a 100644 --- a/artiq/gateware/drtio/link_layer.py +++ b/artiq/gateware/drtio/link_layer.py @@ -56,7 +56,7 @@ class LinkLayerTX(Module): self.submodules += aux_scrambler aux_data_ctl = [] for i in range(nwords): - aux_data_ctl.append(self.aux_data[i*2:i*2+1]) + aux_data_ctl.append(self.aux_data[i*2:i*2+2]) aux_data_ctl.append(0) self.comb += [ If(self.aux_frame, @@ -129,6 +129,7 @@ class LinkLayerRX(Module): self.link_init = Signal() + self.aux_stb = Signal() self.aux_frame = Signal() self.aux_data = Signal(2*nwords) @@ -137,7 +138,7 @@ class LinkLayerRX(Module): # # # - aux_descrambler = ResetInserter()(CEInserter()(Scrambler(2*nwords))) + aux_descrambler = ResetInserter()(CEInserter()(Scrambler(3*nwords))) rt_descrambler = ResetInserter()(CEInserter()(Scrambler(8*nwords))) self.submodules += aux_descrambler, rt_descrambler self.comb += [ @@ -148,9 +149,11 @@ class LinkLayerRX(Module): ] link_init_d = Signal() + aux_stb_d = Signal() rt_frame_d = Signal() self.sync += [ self.link_init.eq(link_init_d), + self.aux_stb.eq(aux_stb_d), self.rt_frame.eq(rt_frame_d) ] @@ -160,12 +163,14 @@ class LinkLayerRX(Module): link_init_d.eq(1), aux_descrambler.reset.eq(1), rt_descrambler.reset.eq(1) + ).Else( + aux_stb_d.eq(1) ), aux_descrambler.ce.eq(1) ).Else( rt_frame_d.eq(1), rt_descrambler.ce.eq(1) ), - aux_descrambler.i.eq(Cat(*[d.d >> 5 for d in decoders])), + aux_descrambler.i.eq(Cat(*[d.d[5:] for d in decoders])), rt_descrambler.i.eq(Cat(*[d.d for d in decoders])) ] diff --git a/artiq/test/gateware/drtio/test_link_layer.py b/artiq/test/gateware/drtio/test_link_layer.py index bb3b71ba5..25a2cd2a0 100644 --- a/artiq/test/gateware/drtio/test_link_layer.py +++ b/artiq/test/gateware/drtio/test_link_layer.py @@ -55,7 +55,8 @@ class TestLinkLayer(unittest.TestCase): rt_packets = [ [0x12459970, 0x9938cdef, 0x12340000], [0xabcdef00, 0x12345678], - [0xeeeeeeee, 0xffffffff, 0x01020304, 0x11223344] + [0xeeeeeeee, 0xffffffff, 0x01020304, 0x11223344], + [0x88277475, 0x19883332, 0x19837662, 0x81726668, 0x81876261] ] def transmit_rt_packets(): while not (yield dut.tx.link_init): @@ -77,22 +78,77 @@ class TestLinkLayer(unittest.TestCase): rx_rt_packets = [] @passive def receive_rt_packets(): + while not (yield dut.rx.link_init): + yield + while (yield dut.rx.link_init): + yield + + previous_frame = 0 + while True: + frame = yield dut.rx.rt_frame + if frame and not previous_frame: + packet = [] + rx_rt_packets.append(packet) + previous_frame = frame + if frame: + packet.append((yield dut.rx.rt_data)) + yield + + aux_packets = [ + [0x12, 0x34], + [0x44, 0x11, 0x98, 0x78], + [0xbb, 0xaa, 0xdd, 0xcc, 0x00, 0xff, 0xee] + ] + def transmit_aux_packets(): while not (yield dut.tx.link_init): yield while (yield dut.tx.link_init): yield + for packet in aux_packets: + yield dut.tx.aux_frame.eq(1) + for data in packet: + yield dut.tx.aux_data.eq(data) + yield + while not (yield dut.tx.aux_ack): + yield + yield dut.tx.aux_frame.eq(0) + yield + while not (yield dut.tx.aux_ack): + yield + # flush + for i in range(20): + yield + + rx_aux_packets = [] + @passive + def receive_aux_packets(): + while not (yield dut.rx.link_init): + yield + while (yield dut.rx.link_init): + yield + + previous_frame = 0 while True: - packet = [] - rx_rt_packets.append(packet) - while not (yield dut.rx.rt_frame): - yield - while (yield dut.rx.rt_frame): - packet.append((yield dut.rx.rt_data)) - yield + if (yield dut.rx.aux_stb): + frame = yield dut.rx.aux_frame + if frame and not previous_frame: + packet = [] + rx_aux_packets.append(packet) + previous_frame = frame + if frame: + packet.append((yield dut.rx.aux_data)) + yield run_simulation(dut, [link_init(), - transmit_rt_packets(), receive_rt_packets()]) + transmit_rt_packets(), receive_rt_packets(), + transmit_aux_packets(), receive_aux_packets()]) - for packet in rx_rt_packets: - print(" ".join("{:08x}".format(x) for x in packet)) + # print("RT:") + # for packet in rx_rt_packets: + # print(" ".join("{:08x}".format(x) for x in packet)) + # print("AUX:") + # for packet in rx_aux_packets: + # print(" ".join("{:02x}".format(x) for x in packet)) + self.assertEqual(rt_packets, rx_rt_packets) + self.assertEqual(aux_packets, rx_aux_packets)