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rtio: support differential ttl

This commit is contained in:
Robert Jördens 2016-10-01 01:26:49 +02:00
parent d0a55e5c9b
commit 95c885b580
1 changed files with 22 additions and 10 deletions
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26
artiq/gateware/rtio/phy/ttl_serdes_7series.py
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@ -4,7 +4,7 @@ from artiq.gateware.rtio.phy import ttl_serdes_generic
class _OSERDESE2_8X(Module):
def __init__(self, pad):
def __init__(self, pad, pad_n=None):
self.o = Signal(8)
self.t_in = Signal()
self.t_out = Signal()
@ -12,20 +12,27 @@ class _OSERDESE2_8X(Module):
# # #
o = self.o
pad_o = Signal()
self.specials += Instance("OSERDESE2",
p_DATA_RATE_OQ="DDR", p_DATA_RATE_TQ="BUF",
p_DATA_WIDTH=8, p_TRISTATE_WIDTH=1,
o_OQ=pad, o_TQ=self.t_out,
o_OQ=pad_o, o_TQ=self.t_out,
i_CLK=ClockSignal("rtiox4"),
i_CLKDIV=ClockSignal("rio_phy"),
i_D1=o[0], i_D2=o[1], i_D3=o[2], i_D4=o[3],
i_D5=o[4], i_D6=o[5], i_D7=o[6], i_D8=o[7],
i_TCE=1, i_OCE=1, i_RST=0,
i_T1=self.t_in)
if pad_n is None:
self.comb += pad.eq(pad_o)
else:
self.specials += Instance("OBUFDS",
i_I=pad_o,
o_O=pad, o_OB=pad_n)
class _IOSERDESE2_8X(Module):
def __init__(self, pad):
def __init__(self, pad, pad_n=None):
self.o = Signal(8)
self.i = Signal(8)
self.oe = Signal()
@ -47,9 +54,14 @@ class _IOSERDESE2_8X(Module):
i_CLKDIV=ClockSignal("rio_phy"))
oserdes = _OSERDESE2_8X(pad_o)
self.submodules += oserdes
if pad_n is None:
self.specials += Instance("IOBUF",
i_I=pad_o, o_O=pad_i, i_T=oserdes.t_out,
io_IO=pad)
else:
self.specials += Instance("IOBUFDS",
i_I=pad_o, o_O=pad_i, i_T=oserdes.t_out,
io_IO=pad, io_IOB=pad_n)
self.comb += [
oserdes.t_in.eq(~self.oe),
oserdes.o.eq(self.o)
@ -57,14 +69,14 @@ class _IOSERDESE2_8X(Module):
class Output_8X(ttl_serdes_generic.Output):
def __init__(self, pad):
serdes = _OSERDESE2_8X(pad)
def __init__(self, pad, pad_n=None):
serdes = _OSERDESE2_8X(pad, pad_n)
self.submodules += serdes
ttl_serdes_generic.Output.__init__(self, serdes)
class Inout_8X(ttl_serdes_generic.Inout):
def __init__(self, pad):
serdes = _IOSERDESE2_8X(pad)
def __init__(self, pad, pad_n=None):
serdes = _IOSERDESE2_8X(pad, pad_n)
self.submodules += serdes
ttl_serdes_generic.Inout.__init__(self, serdes)